JP4442560B2 - Ｓｏｉウエーハの製造方法 - Google Patents

Ｓｏｉウエーハの製造方法 Download PDF

Info

Publication number
JP4442560B2
JP4442560B2 JP2005502689A JP2005502689A JP4442560B2 JP 4442560 B2 JP4442560 B2 JP 4442560B2 JP 2005502689 A JP2005502689 A JP 2005502689A JP 2005502689 A JP2005502689 A JP 2005502689A JP 4442560 B2 JP4442560 B2 JP 4442560B2
Authority
JP
Japan
Prior art keywords
oxide film
buried oxide
thickness
heat treatment
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005502689A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2004075298A1 (ja
Inventor
功 横川
浩司 阿賀
清隆 高野
清 三谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of JPWO2004075298A1 publication Critical patent/JPWO2004075298A1/ja
Application granted granted Critical
Publication of JP4442560B2 publication Critical patent/JP4442560B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
JP2005502689A 2003-02-19 2004-02-13 Ｓｏｉウエーハの製造方法 Expired - Fee Related JP4442560B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003040875 2003-02-19
JP2003040875 2003-02-19
PCT/JP2004/001557 WO2004075298A1 (ja) 2003-02-19 2004-02-13 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ

Publications (2)

Publication Number Publication Date
JPWO2004075298A1 JPWO2004075298A1 (ja) 2006-06-01
JP4442560B2 true JP4442560B2 (ja) 2010-03-31

Family

ID=32905270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005502689A Expired - Fee Related JP4442560B2 (ja) 2003-02-19 2004-02-13 Ｓｏｉウエーハの製造方法

Country Status (7)

Country Link
US (1) US7524744B2 (enExample)
EP (1) EP1596437A4 (enExample)
JP (1) JP4442560B2 (enExample)
KR (1) KR100947815B1 (enExample)
CN (1) CN100418194C (enExample)
TW (1) TW200416814A (enExample)
WO (1) WO2004075298A1 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5054509B2 (ja) * 2004-02-25 2012-10-24 ソワテク 光検出装置
JP5374805B2 (ja) * 2006-03-27 2013-12-25 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法
EP2012347B1 (en) 2006-04-24 2015-03-18 Shin-Etsu Handotai Co., Ltd. Method for producing soi wafer
CN101548369B (zh) * 2006-12-26 2012-07-18 硅绝缘体技术有限公司 制造绝缘体上半导体结构的方法
DE602006017906D1 (de) * 2006-12-26 2010-12-09 Soitec Silicon On Insulator Verfahren zum herstellen einer halbleiter-auf-isolator-struktur
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
WO2008096194A1 (en) 2007-02-08 2008-08-14 S.O.I.Tec Silicon On Insulator Technologies Method of fabrication of highly heat dissipative substrates
KR101431780B1 (ko) 2007-03-19 2014-09-19 소이텍 패턴화된 얇은 ｓｏｉ
JP2011504655A (ja) * 2007-11-23 2011-02-10 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 精密な酸化物の溶解
US8148242B2 (en) 2008-02-20 2012-04-03 Soitec Oxidation after oxide dissolution
JP2010027959A (ja) * 2008-07-23 2010-02-04 Sumco Corp 高抵抗ｓｉｍｏｘウェーハの製造方法
JP5493345B2 (ja) * 2008-12-11 2014-05-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
KR100987794B1 (ko) 2008-12-22 2010-10-13 한국전자통신연구원 반도체 장치의 제조 방법
US8168507B2 (en) 2009-08-21 2012-05-01 International Business Machines Corporation Structure and method of forming enhanced array device isolation for implanted plate EDRAM
CN101958317A (zh) * 2010-07-23 2011-01-26 上海宏力半导体制造有限公司 一种晶圆结构及其制造方法
FR2964495A1 (fr) * 2010-09-02 2012-03-09 Soitec Silicon On Insulator Procede de fabrication d'une structure seoi multiple comportant une couche isolante ultrafine
FR2972564B1 (fr) 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
FR2998418B1 (fr) * 2012-11-20 2014-11-21 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur sur isolant
CN105009297B (zh) * 2013-03-12 2019-06-14 应用材料公司 用于金属氧化物半导体薄膜晶体管的介电薄膜的针孔评估方法
CN103579109B (zh) * 2013-11-01 2016-06-08 电子科技大学 一种光电集成电路的制造方法
CN107393863A (zh) * 2017-05-22 2017-11-24 茆胜 Oled微型显示器ic片及其制备方法
CN109496368A (zh) * 2018-10-12 2019-03-19 京东方科技集团股份有限公司 微发光二极管装置及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310689A (en) * 1990-04-02 1994-05-10 Motorola, Inc. Method of forming a SIMOX structure
JP3036619B2 (ja) 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
US5893729A (en) * 1995-06-28 1999-04-13 Honeywell Inc. Method of making SOI circuit for higher temperature and higher voltage applications
US5712173A (en) * 1996-01-24 1998-01-27 Advanced Micro Devices, Inc. Method of making semiconductor device with self-aligned insulator
US5795813A (en) * 1996-05-31 1998-08-18 The United States Of America As Represented By The Secretary Of The Navy Radiation-hardening of SOI by ion implantation into the buried oxide layer
JPH1079355A (ja) * 1996-09-03 1998-03-24 Komatsu Denshi Kinzoku Kk Ｓｏｉ基板の製造方法
JP3762144B2 (ja) * 1998-06-18 2006-04-05 キヤノン株式会社 Ｓｏｉ基板の作製方法
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP2000082679A (ja) 1998-07-08 2000-03-21 Canon Inc 半導体基板とその作製方法
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000091406A (ja) * 1998-09-08 2000-03-31 Mitsubishi Materials Silicon Corp ウェーハ保持具
FR2784796B1 (fr) * 1998-10-15 2001-11-23 Commissariat Energie Atomique Procede de realisation d'une couche de materiau enterree dans un autre materiau
JP2001144275A (ja) 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウエーハの製造方法および貼り合わせｓｏｉウエーハ
JP3910766B2 (ja) 1999-09-16 2007-04-25 日野自動車株式会社 車高調整装置
JP2001257329A (ja) * 2000-03-10 2001-09-21 Nippon Steel Corp Ｓｉｍｏｘ基板およびその製造方法
US6417078B1 (en) * 2000-05-03 2002-07-09 Ibis Technology Corporation Implantation process using sub-stoichiometric, oxygen doses at different energies
US6461933B2 (en) * 2000-12-30 2002-10-08 Texas Instruments Incorporated SPIMOX/SIMOX combination with ITOX option
JP2002270614A (ja) * 2001-03-12 2002-09-20 Canon Inc Ｓｏｉ基体、その熱処理方法、それを有する半導体装置およびその製造方法
US20020190318A1 (en) 2001-06-19 2002-12-19 International Business Machines Corporation Divot reduction in SIMOX layers
US20050170570A1 (en) * 2004-01-30 2005-08-04 International Business Machines Corporation High electrical quality buried oxide in simox

Also Published As

Publication number Publication date
EP1596437A1 (en) 2005-11-16
EP1596437A4 (en) 2009-12-02
WO2004075298A1 (ja) 2004-09-02
CN1748312A (zh) 2006-03-15
KR20050100665A (ko) 2005-10-19
US7524744B2 (en) 2009-04-28
US20060051945A1 (en) 2006-03-09
TWI344667B (enExample) 2011-07-01
KR100947815B1 (ko) 2010-03-15
JPWO2004075298A1 (ja) 2006-06-01
CN100418194C (zh) 2008-09-10
TW200416814A (en) 2004-09-01

Similar Documents

Publication Publication Date Title
JP4442560B2 (ja) Ｓｏｉウエーハの製造方法
TWI310962B (enExample)
JP4509488B2 (ja) 貼り合わせ基板の製造方法
CN100372060C (zh) 半导体材料的膜或层及制造该膜或层的方法
JP3395661B2 (ja) Ｓｏｉウエーハの製造方法
US6313014B1 (en) Semiconductor substrate and manufacturing method of semiconductor substrate
US8173521B2 (en) Method for manufacturing bonded wafer
EP3104395B1 (en) Method for manufacturing laminated wafer
JP4820801B2 (ja) 貼り合わせウェーハの製造方法
US7947571B2 (en) Method for fabricating a semiconductor on insulator substrate with reduced Secco defect density
EP3118889B1 (en) Process for producing bonded soi wafer
JP5522175B2 (ja) Ｓｏｉウェーハの製造方法
JP5320954B2 (ja) Ｓｏｉウェーハの製造方法
US20190198386A1 (en) Method for manufacturing bonded soi wafer
KR101543748B1 (ko) Ｓｏｉ 웨이퍼의 제조방법
CN105264641B (zh) 贴合晶圆的制造方法
JP4529036B2 (ja) 半導体用薄膜ウェハの製造方法
JP2007242972A (ja) Ｓｏｉウェーハの製造方法
JP2010135538A (ja) 貼り合わせウェーハの製造方法
JP2003179216A (ja) Ｓｏｉウエーハ
JP2006013179A (ja) Ｓｏｉウェーハの製造方法
JP2004087767A (ja) Ｓｏｉウエーハの製造方法

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090609

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090713

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091222

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100104

R150 Certificate of patent or registration of utility model

Ref document number: 4442560

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130122

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130122

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140122

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees