JP4331966B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP4331966B2
JP4331966B2 JP2003108604A JP2003108604A JP4331966B2 JP 4331966 B2 JP4331966 B2 JP 4331966B2 JP 2003108604 A JP2003108604 A JP 2003108604A JP 2003108604 A JP2003108604 A JP 2003108604A JP 4331966 B2 JP4331966 B2 JP 4331966B2
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JP
Japan
Prior art keywords
bit line
memory
read
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003108604A
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English (en)
Japanese (ja)
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JP2004318941A (ja
JP2004318941A5 (https=
Inventor
正道 藤戸
裕 品川
一文 鈴川
綾子 佐野
章 加藤
利広 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2003108604A priority Critical patent/JP4331966B2/ja
Priority to US10/810,672 priority patent/US7190615B2/en
Priority to TW093109996A priority patent/TW200504757A/zh
Priority to KR1020040024833A priority patent/KR20040090425A/ko
Publication of JP2004318941A publication Critical patent/JP2004318941A/ja
Publication of JP2004318941A5 publication Critical patent/JP2004318941A5/ja
Priority to US11/713,039 priority patent/US7342826B2/en
Application granted granted Critical
Publication of JP4331966B2 publication Critical patent/JP4331966B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

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  • Read Only Memory (AREA)
JP2003108604A 2003-04-14 2003-04-14 半導体集積回路 Expired - Lifetime JP4331966B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003108604A JP4331966B2 (ja) 2003-04-14 2003-04-14 半導体集積回路
US10/810,672 US7190615B2 (en) 2003-04-14 2004-03-29 Semiconductor device
TW093109996A TW200504757A (en) 2003-04-14 2004-04-09 Semiconductor integrated circuit
KR1020040024833A KR20040090425A (ko) 2003-04-14 2004-04-12 반도체 집적회로
US11/713,039 US7342826B2 (en) 2003-04-14 2007-03-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003108604A JP4331966B2 (ja) 2003-04-14 2003-04-14 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009116104A Division JP2009176419A (ja) 2009-05-13 2009-05-13 データ処理装置

Publications (3)

Publication Number Publication Date
JP2004318941A JP2004318941A (ja) 2004-11-11
JP2004318941A5 JP2004318941A5 (https=) 2006-04-13
JP4331966B2 true JP4331966B2 (ja) 2009-09-16

Family

ID=33128070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003108604A Expired - Lifetime JP4331966B2 (ja) 2003-04-14 2003-04-14 半導体集積回路

Country Status (4)

Country Link
US (2) US7190615B2 (https=)
JP (1) JP4331966B2 (https=)
KR (1) KR20040090425A (https=)
TW (1) TW200504757A (https=)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW546840B (en) 2001-07-27 2003-08-11 Hitachi Ltd Non-volatile semiconductor memory device
KR100587702B1 (ko) * 2004-07-09 2006-06-08 삼성전자주식회사 피크 전류의 감소 특성을 갖는 상변화 메모리 장치 및그에 따른 데이터 라이팅 방법
WO2006018862A1 (ja) * 2004-08-16 2006-02-23 Fujitsu Limited 不揮発性半導体メモリ
JP2007133927A (ja) * 2005-11-08 2007-05-31 Toshiba Corp 半導体記憶装置及びその制御方法
KR100735612B1 (ko) 2005-12-22 2007-07-04 삼성전자주식회사 멀티패쓰 억세스블 반도체 메모리 장치
JP2007200512A (ja) 2006-01-30 2007-08-09 Renesas Technology Corp 半導体記憶装置
US8010867B2 (en) * 2006-10-12 2011-08-30 Renesas Electronics Corporation Error correction code decoding device
KR100914265B1 (ko) * 2007-05-10 2009-08-27 삼성전자주식회사 비휘발성 메모리 장치, 그것을 포함한 메모리 시스템 및그것의 읽기 방법
US7643367B2 (en) * 2007-08-15 2010-01-05 Oki Semiconductor Co., Ltd. Semiconductor memory device
US7800951B2 (en) 2007-08-20 2010-09-21 Marvell World Trade Ltd. Threshold voltage digitizer for array of programmable threshold transistors
JP2009123298A (ja) 2007-11-16 2009-06-04 Renesas Technology Corp 半導体集積回路装置
JP2009146499A (ja) * 2007-12-13 2009-07-02 Toshiba Corp 不揮発性メモリカード
JP4907563B2 (ja) * 2008-01-16 2012-03-28 パナソニック株式会社 半導体記憶装置
KR101452957B1 (ko) 2008-02-21 2014-10-21 삼성전자주식회사 리드 와일 라이트 동작시 커플링 노이즈를 방지할 수 있는상 변화 메모리 장치
JP5777845B2 (ja) * 2008-06-26 2015-09-09 スパンション エルエルシー 不揮発性記憶装置及び不揮発性記憶装置からのデータ読み出し方法
US8228714B2 (en) * 2008-09-09 2012-07-24 Qualcomm Incorporated Memory device for resistance-based memory applications
US8259461B2 (en) 2008-11-25 2012-09-04 Micron Technology, Inc. Apparatus for bypassing faulty connections
US8645617B2 (en) * 2008-12-09 2014-02-04 Rambus Inc. Memory device for concurrent and pipelined memory operations
JP5197406B2 (ja) * 2009-01-27 2013-05-15 株式会社東芝 半導体記憶装置
US7936625B2 (en) * 2009-03-24 2011-05-03 Seagate Technology Llc Pipeline sensing using voltage storage elements to read non-volatile memory cells
US8098507B2 (en) * 2009-07-13 2012-01-17 Seagate Technology Llc Hierarchical cross-point array of non-volatile memory
US8363450B2 (en) 2009-07-13 2013-01-29 Seagate Technology Llc Hierarchical cross-point array of non-volatile memory
JP5528869B2 (ja) * 2010-03-23 2014-06-25 スパンション エルエルシー 不揮発性半導体記憶装置及びその読み出し方法
JP5343916B2 (ja) 2010-04-16 2013-11-13 富士通セミコンダクター株式会社 半導体メモリ
JP5972700B2 (ja) * 2012-07-31 2016-08-17 ルネサスエレクトロニクス株式会社 メモリ装置
KR20150033374A (ko) 2013-09-24 2015-04-01 에스케이하이닉스 주식회사 반도체 시스템 및 반도체 장치
US9431111B2 (en) * 2014-07-08 2016-08-30 Ememory Technology Inc. One time programming memory cell, array structure and operating method thereof
JP6422273B2 (ja) * 2014-09-03 2018-11-14 ルネサスエレクトロニクス株式会社 半導体装置
US9653174B2 (en) 2015-03-10 2017-05-16 Kabushiki Kaisha Toshiba Semiconductor storage device
KR102671075B1 (ko) * 2017-01-13 2024-05-30 에스케이하이닉스 주식회사 반도체장치
JP6846321B2 (ja) 2017-09-21 2021-03-24 ルネサスエレクトロニクス株式会社 半導体記憶装置、及び半導体記憶装置の制御方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3579205B2 (ja) * 1996-08-06 2004-10-20 株式会社ルネサステクノロジ 半導体記憶装置、半導体装置、データ処理装置及びコンピュータシステム
JP3602939B2 (ja) * 1996-11-19 2004-12-15 松下電器産業株式会社 半導体記憶装置
JP3990485B2 (ja) * 1997-12-26 2007-10-10 株式会社ルネサステクノロジ 半導体不揮発性記憶装置
JP2000048586A (ja) * 1998-07-30 2000-02-18 Fujitsu Ltd 不揮発性半導体記憶装置
JP2000339983A (ja) 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体集積回路装置
US6275407B1 (en) * 1999-06-29 2001-08-14 Kabushiki Kaisha Toshiba Semiconductor memory device having sense and data lines for use to read and write operations
JP2001084776A (ja) * 1999-09-17 2001-03-30 Toshiba Corp 半導体記憶装置
JP5034133B2 (ja) * 2000-02-29 2012-09-26 富士通セミコンダクター株式会社 半導体記憶装置
US6704828B1 (en) * 2000-08-31 2004-03-09 Micron Technology, Inc. System and method for implementing data pre-fetch having reduced data lines and/or higher data rates
JP2002133873A (ja) * 2000-10-23 2002-05-10 Matsushita Electric Ind Co Ltd 半導体記憶装置
US6760243B2 (en) * 2002-03-19 2004-07-06 Broadcom Corporation Distributed, highly configurable modular predecoding
JP2004213829A (ja) * 2003-01-08 2004-07-29 Renesas Technology Corp 半導体記憶装置
US7158429B1 (en) * 2003-03-26 2007-01-02 Cypress Semiconductor Corp. System for read path acceleration
JP2005004835A (ja) * 2003-06-10 2005-01-06 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR20040090425A (ko) 2004-10-22
US7190615B2 (en) 2007-03-13
US20040202020A1 (en) 2004-10-14
TWI360819B (https=) 2012-03-21
US20070153618A1 (en) 2007-07-05
TW200504757A (en) 2005-02-01
JP2004318941A (ja) 2004-11-11
US7342826B2 (en) 2008-03-11

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