JP4312734B2 - 半導体チップのための回路担体および構造素子 - Google Patents
半導体チップのための回路担体および構造素子 Download PDFInfo
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- JP4312734B2 JP4312734B2 JP2005108963A JP2005108963A JP4312734B2 JP 4312734 B2 JP4312734 B2 JP 4312734B2 JP 2005108963 A JP2005108963 A JP 2005108963A JP 2005108963 A JP2005108963 A JP 2005108963A JP 4312734 B2 JP4312734 B2 JP 4312734B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 230000001070 adhesive effect Effects 0.000 claims description 64
- 239000000853 adhesive Substances 0.000 claims description 63
- 230000004308 accommodation Effects 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 239000000945 filler Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000011109 contamination Methods 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000009830 intercalation Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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Description
Claims (13)
- 絶縁材料からなる基板(1)を備え、
この基板上にチップ収容範囲(2)およびこのチップ収容範囲を包囲する多数の結合パッド(5)が同一平面上に配置されており、チップ収容範囲(2)の中心範囲(14)にチップ(6)を取り付けることができる、半導体チップ(6)のための回路担体において、チップ収容範囲(2)が中心範囲(14)を包囲する縁部範囲(15)を有し、縁部範囲(15)がチップ収容範囲(2)の縁部曲線を定義し、この縁部曲線が取り付けるべきチップ(6)の側方縁部(10)の長さと比較して付着力の形成を可能にするような長さを有し、この付着力が結合パッド(5)の方向でのチップ収容範囲(2)の縁部上への付着剤(11)の流れを阻止することを特徴とする、半導体チップ(6)のための回路担体。 - チップ収容範囲(2)の縁部範囲(15)に幾何学的形状の縁部構造素子(3)が設けられている、請求項1記載の回路担体。
- 中心範囲(14)が縁部(9)によって定義されており、この縁部がチップ(6)の側方縁部(10)の曲線にほぼ適合しており、縁部構造素子(3)が少なくとも1つの縁部(9)に沿って配置されている、請求項1または2記載の回路担体。
- 中心範囲(14)の角に縁部構造角部素子(4)が配置されている、請求項1から3までのいずれか1項に記載の回路担体。
- 縁部構造素子(3)および/または縁部構造角部素子(4)が多角形または"T字形"の形状を有するかまたは湾曲した形で形成されている、請求項2から4までのいずれか1項に記載の回路担体。
- 縁部構造素子(3)および/または縁部構造角部素子(4)が少なくとも1つの破断部を有する、請求項5記載の回路担体。
- 2個の縁部構造素子(3)および/または1個の縁部構造素子(3)と1個の縁部構造角部素子(4)とが距離をおいて互いに配置されている、請求項5記載の回路担体。
- 2個の縁部構造素子(3)および/または1個の縁部構造素子(3)と1個の縁部構造角部素子(4)とが互いに境界で接するように互いに配置されている、請求項5記載の回路担体。
- 縁部構造素子(3)が結合パッド(5)の1つと向かい合うように配置されている、請求項2記載の回路担体。
- 結合パッドが互いに距離をおいて基板上に取り付けられており、したがってそれぞれ2個の隣接した結合パッドの間には、中間空間(13)が形成されており、縁部構造素子(3)が中間空間(13)の1つに向かい合って配置されている、請求項2記載の回路担体。
- 結合パッド(5)が中心範囲(14)の縁部(9)と距離(16)をおいて配置されており、縁部構造素子(3)が結合パッド(5)の方向で縁部(9)からの距離(16)に対して25〜50%の最大の伸びを有する、請求項2記載の回路担体。
- 請求項1から11までのいずれか1項に記載の回路担体(20)のチップ収容範囲(2)上に取り付けられている半導体チップ(6)を有する構造素子。
- 半導体チップ(6)を固定するための付着剤として、少なくとも1つの樹脂成分および少なくとも1つの充填剤を有する接着剤が設けられている、請求項12記載の構造素子。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004016940.3A DE102004016940B4 (de) | 2004-04-06 | 2004-04-06 | Schaltungsträger für einen Halbleiterchip und ein Bauelement mit einem Halbleiterchip |
Publications (2)
Publication Number | Publication Date |
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JP2005303296A JP2005303296A (ja) | 2005-10-27 |
JP4312734B2 true JP4312734B2 (ja) | 2009-08-12 |
Family
ID=35053387
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Application Number | Title | Priority Date | Filing Date |
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JP2005108963A Expired - Fee Related JP4312734B2 (ja) | 2004-04-06 | 2005-04-05 | 半導体チップのための回路担体および構造素子 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7256504B2 (ja) |
JP (1) | JP4312734B2 (ja) |
DE (1) | DE102004016940B4 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006132130A1 (ja) | 2005-06-06 | 2006-12-14 | Rohm Co., Ltd. | 半導体装置、基板および半導体装置の製造方法 |
DE102017215048A1 (de) * | 2017-08-29 | 2019-02-28 | Conti Temic Microelectronic Gmbh | Schaltungsträger für Leistungselektronik und Leistungselektronikmodul mit einem Schaltungsträger |
DE102019104334A1 (de) * | 2019-02-20 | 2020-08-20 | Infineon Technologies Ag | Halbleiteranordnung und verfahren zum herstellen einer hableiteranordnung |
DE102020126376A1 (de) | 2020-10-08 | 2022-04-14 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Elektrische kontaktanordnung, verfahren für deren herstellung und diese umfassendes optoelektronisches bauteil |
CN114039219A (zh) * | 2022-01-10 | 2022-02-11 | 珠海华萃科技有限公司 | 一种电子元器件焊锡用防漂移结构 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0364056A (ja) | 1989-08-01 | 1991-03-19 | Mitsubishi Electric Corp | 半導体装置 |
JPH0423441A (ja) | 1990-05-18 | 1992-01-27 | Fujitsu Ltd | セラミックパッケージ半導体装置およびその製造方法 |
JPH06342817A (ja) | 1993-06-02 | 1994-12-13 | Seiko Epson Corp | 半導体装置 |
US6204555B1 (en) | 1996-10-10 | 2001-03-20 | Samsung Electronics Co., Ltd. | Microwave-frequency hybrid integrated circuit |
JPH10163407A (ja) | 1996-11-26 | 1998-06-19 | New Japan Radio Co Ltd | 半導体装置用リードフレーム及び半導体装置 |
JP2001351929A (ja) * | 2000-06-09 | 2001-12-21 | Hitachi Ltd | 半導体装置およびその製造方法 |
SG97938A1 (en) * | 2000-09-21 | 2003-08-20 | Micron Technology Inc | Method to prevent die attach adhesive contamination in stacked chips |
JP3913574B2 (ja) * | 2002-02-27 | 2007-05-09 | 三洋電機株式会社 | 半導体装置 |
TWI242274B (en) * | 2003-02-27 | 2005-10-21 | Siliconware Precision Industries Co Ltd | Ball grid array semiconductor package and method for fabricating the same |
US8536688B2 (en) * | 2004-05-25 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit leadframe and fabrication method therefor |
-
2004
- 2004-04-06 DE DE102004016940.3A patent/DE102004016940B4/de not_active Expired - Fee Related
-
2005
- 2005-04-05 JP JP2005108963A patent/JP4312734B2/ja not_active Expired - Fee Related
- 2005-04-06 US US11/099,823 patent/US7256504B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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DE102004016940A1 (de) | 2005-10-27 |
US20050218529A1 (en) | 2005-10-06 |
US7256504B2 (en) | 2007-08-14 |
DE102004016940B4 (de) | 2019-08-08 |
JP2005303296A (ja) | 2005-10-27 |
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