JPH0423441A - セラミックパッケージ半導体装置およびその製造方法 - Google Patents

セラミックパッケージ半導体装置およびその製造方法

Info

Publication number
JPH0423441A
JPH0423441A JP2129712A JP12971290A JPH0423441A JP H0423441 A JPH0423441 A JP H0423441A JP 2129712 A JP2129712 A JP 2129712A JP 12971290 A JP12971290 A JP 12971290A JP H0423441 A JPH0423441 A JP H0423441A
Authority
JP
Japan
Prior art keywords
stage
semiconductor chip
package
ceramic
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2129712A
Other languages
English (en)
Inventor
Ichiro Yamaguchi
一郎 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2129712A priority Critical patent/JPH0423441A/ja
Priority to EP91107761A priority patent/EP0457260A1/en
Priority to US07/700,777 priority patent/US5091770A/en
Priority to KR91007930A priority patent/KR940008553B1/ko
Publication of JPH0423441A publication Critical patent/JPH0423441A/ja
Pending legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/166—Material
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 「概要コ エポキシ系ペーストでダイス付けするセラミックパッケ
ージ半導体装置とその製造方法に関し、エポキシ系ダイ
ス付は材を用い、かつボンディング不良の少ないセラミ
ックパッケージ半導体装置を提供することを目的とし、 セラミック製のパッケージであって、半導体チップを載
置するステージ中央部と少なくとも該ステージの一辺と
の間のステージ周縁部に表面が溶融された溶融帯を有し
、溶融帯の外側にインナーリードを有するパッケージと
、パッケージのステージに樹脂でダイス付けされ、表面
にホンディングパッドを有する半導体チップと、半導体
チップ−Ｆのボンディングパッドとパッケージ上のイン
ナーリードとを接続するボンディングワイヤとを含むよ
うに構成する。
［産業上の利用分野］ 本発明は半導体装置とその製造方法に関し、特にエポキ
シ系ペーストでダイス付けするセラミックパッケージ半
導体装置とその製造方法に関する。
［従来の技術］ 近年、ＩＣに対するコスｌ〜タウンの要求に沿って、Ａ
ｕＳ　ｉダイス付は材に代って、エポキシ、系ペースト
のダイス付は材の使用か増加している。
多孔質セラミックパッケージにエポキシ系ペーストをダ
イス付は材として用いて半導体チップをダイス付けする
と、ペースト成分中の樹脂分が多孔質セラミックの毛細
管現象によって周囲に染み出す。この現象はブリーディ
ングと呼ばれる。セラミックを用いる場合、ブリーディ
ングは免れ雛い。
第２図に従来の技術を示す。多孔質セラミックのパッケ
ージ１のステージ２に半導体チップ５がエポキシ系ペー
ストのダイス付は材６によってダイス付けされている。
ダイス付は材６から樹脂分が染み出し、周囲に拡がって
ブリーディング８を形成している。インナーリード１０
に達したブリーディング８は、インナーリード１０表面
上にも這い上かっている。この状態でワイヤボンディン
グすると、インナーリード側ではボンディング不良を起
こす。
「発明が解決しようとする課題］ エポキシ系ダイス付は材等の樹脂をダイス付けに用いた
場合、ブリーディングの幅は通常かなり広く、パッケー
ジのステージから周辺に拡がってインナーリード表面に
達することもある。するとインナーリード表面に樹脂分
か付着することになる。この様なインナーリードにワイ
ヤボンディングを行うと、ホンディング不良を起こす。
本発明の目的は、樹脂ダイス付は材を用い、かつホンデ
ィング不良の少ないセラミックパッケージ半導体装置を
提供することである。
本発明の他の目的は、樹脂ダイス付は材を用いてダイス
付けを行っても、ブリーディングか制限されるセラミッ
クパッケージ半導体装置の製造方法を提供することであ
る。
［課題を解決するための手段］ 第１図は、本発明の原理説明図である。
セラミック製のパッケージ１は半導体チップを載置する
ためのステージ２を有する。半導体チップを載置するス
テージ中央部と、少なくともその一辺との間に表面か溶
融された溶融帯３が形成されている。この溶融帯３に関
し、半導体チップ５と反対側にインナーリード１０が形
成されている。
半導体チップ５は、ステージ２にダイス付は材６でダイ
ス付けされている。ダイス付は材６は樹脂を含み、その
下にブリーディング８を生じている。
ブリーディングは溶融帯３の反対側においてはあまり発
達していない。半導体チップ５表面上のボンデインクパ
ッド４とインナーリード１０との間は、ポンディングワ
イヤ９によってワイヤボンデインクされている。
このような半導体装置を製作するには、先ずセラミック
製のパッケージ１のステージ周辺部をレーザビームによ
って溶融し、溶融帯を形成した後、ダイス付けを行う。
ダイス付けを行った後、半導体チップ上のホンディング
パッドとインナーリードとの間のワイヤボンティングを
行なう。
［作用］ セラミックは、その性質上、特に表面に沿って毛細管現
象を生じる。ダイス付は材としてエポキシ系ペースト等
の樹脂を用いると、樹脂分か特にセラミック表面の毛細
管現象によって、周囲に染み出しを起こす。レーザビー
ムによって、セラミックパッケージの表面を溶融すると
、未処理の領域とは異なるより滑らかな表面を有する溶
融帯か形成される。この溶融帯は、樹脂分のブリーディ
ングに対し、より大きな抵抗を示す６従って、半導体チ
ップとインナーリードとの間に溶融帯を形成することに
より、ブリーディングを低減することかでき、ワイヤボ
ンディングを確実に行うことか可能となる。
［実施例］ 第３図（Ａ）、（Ｂ）に、本発明の実施例による多孔質
セラミックパッケージ半導体装置を示す。
第３し１（Ａ）は断面構造を示し、第３図（Ｂ）は平面
構造を概略的に示す。
アルミナセラミック等の多孔質セラミックで形成された
パンケージ本体１１は、その中央部にＩＣ等の半導体チ
ップを載置するためのステージ１２を有する。ステージ
１２の周縁部には、第３図（Ｂ）に示ずように、レーザ
ビームで溶融された溶融帯１３かループ状に形成されて
いる。ＩＣチップ１５は、ステージ１２中央部にダイス
付は材１６によってダイス付けされる。ここで、ＩＣチ
ップ１５とインナーリード２０との間には、必ず溶融帯
１３か存在するようにする。溶融帯１３をループ状に形
成した場合は、その内側にＩＣチップ１５を配置ずれば
よい、ダイス付は後、ＩＣチップ１５」二のボンデイン
クパッド１４とパッケージ本体１１上のインナーリード
２０との間をホンディングワイヤ１つでワイヤボンディ
ングすることにより、配線を形成する。インナーリード
２０は、第３図（Ｂ）に示すインナーリード領域２２に
配置される２インナーリード領域の４辺全てにインナー
リード２０か配置される構成を示しなか、その一部にイ
ンナーリードを配するものであってもよい。ワイヤボン
ディング後、パッケージ蓋体２１をパッケージ本体１１
にシールすることにより、半導体装置が完成する。
溶融帯１３は、ブリーディングに対して強い抵抗を示す
。従って、ダイス付は材中の樹脂分がＩＣチップ１５下
方から周囲にブリーディングで広かろうとする時、溶融
帯１３によってそのブリーディングの程度が低減される
。たとえば、溶融帯１３を幅約１．ｍｌ程度以上形成す
ることにより、溶融帯１３の外側に染み出ずブリーディ
ングの幅は、はとんど無視できる程度にできる。溶融帯
１３の表面は、未処理の時の光散乱性表面から−カラス
的な濡れた面になることか好ましい。
第４図に本発明の他の実施例を示す。本実施例において
は、インナーリード領域２２の対向する２辺の上にのみ
インナーリード２０が形成されている。そのため、ステ
ージ１２中央部にＩＣチップを載置した時、ＩＣチップ
とインナーリードとの間に挾まれる領域は、４辺の内２
辺のみである。
従って、フリーデインク対策もこの２辺において行えば
足り、ステージ１２のインナーリードを設けた側の周縁
部にス）〜ライプ状の溶融帯１３か設けられている。こ
のストライプ状の溶融帯１３は対向する２辺の上にのみ
設けられており、他の２辺の上には存在しない。
第４図の構成においては、不要な溶融帯を省略すること
により、製造工程か簡略化される。
第３図、第４図に示したような半導体装置を製造する方
法を、第５図（Ａ、）〜（Ｄ）を参照して説明する。
第５図（Ａ）に示すように、アルミナセラミック等の多
孔質セラミックで形成されたパッケージ本体１１のステ
ージ周縁部の所望領域に、レーザビームを照射する。１
例においては、発振波長１゜０６μｍ、発振電流１２Ａ
、発振周波数５ＫＨ２のＹＡＧレーザビーム２５を照射
し、約１０ｍｍ／　ｓ　ｅ　ｃの速度で走査した。ＹＡ
Ｇレーザビームのパワーは、セラミックパッケージ本体
１１の表面を溶融するのに十分なように選ぶ、パッケー
ジ本体１１の表面が溶融し、溶融領域２６が発生する。
レーザビーム２５を走査することによって、溶融領域２
６も移動する。好ましくは、幅約１ｎｏｎ以上の溶融帯
を形成する。
その後、第５図（Ｂ）に示すように、ＩＣチップ１５を
エポキシ系ペーストのダイス付は材１６によってステー
ジ１２中央部にダイス付けする４エポキシ系ペーストの
ダイス付は材１６はブリーディングを起こすが、溶融帯
１３によってブリーディングの拡がりが制限されるため
、インナーリード領域２２にブリーディングが及ぶこと
が防止される。
ダイス付は後−第５図（Ｃ）に示すように、１Ｃチップ
１５とパッケージ上のインナーリードとの間をＡ９等の
ホンディングワイヤ１９でワイヤボンディングする。
その後、アルミナセラミック等のセラミック製パッケー
ジ藍体２１をパッケージ本体１１にシールすることによ
り、半導体装置が完成する。
なお、レーザ照射によって形成される溶融帯は、深さ数
μｍに及ぶものと考えられる６溶融帯の幅は余り狭いと
、ブリーディング防止効果が低いが、約１ｍｌ程度の幅
とすることにより、ブリーディングは顕著に抑制される
。レーザビームはＹＡＧのほか、セラミックパッケージ
を溶融できるものであれば、どのようなレーザビームで
あてもよいものと考えられる。
溶融帯によるブリーディング抑制の効果のテストを行な
った効果を第６図に概略的に示す。第６図（Ａ）は溶融
帯がない場合、第６図（Ｂ）は約１ｍｍ幅の溶融帯を形
成した場合を示す。溶融帯がない時、ブリーディング８
は第６図（Ａ）に示すようにほぼ等友釣に拡がる。溶融
帯１３を形成すると、ブリーディング８は大巾に抑制さ
れ、溶融帯を貫通してもブリーディング８ａのようにか
なり小さなものとなる。
以上、限られた実施例について本発明を説明したが、本
発明はこれらに制限されるものではない。
たとえば、種々の変更、改良、組み合わせ等が可能なこ
とは、当業者に自明であろう。
［発明の効果］ 以上説明したように、本発明によれば、セラミックパッ
ケージを用い、樹脂で半導体チップをダイス付けしても
、ブリーディングが抑制されるため、ホンディング不良
を起こすことが防止できる。
【図面の簡単な説明】
第１図は本発明の原理説明図、 第２図は従来の技術を示す断面図、 第３図（Ａ）、（Ｂ）は、本発明の実施例による半導体
装置の断面図と平面図、 第４図は本発明の他の実施例による半導体装置を説明す
るための平面図、 第５図（Ａ）〜（Ｄ）は、本発明の実施例による半導体
装置の製造方法を説明するための断面図、第６図（Ａ）
、（Ｂ）は溶融帯の有無によるブリーディングの実験結
果を概略的に示す平面図である。 図において、 パッケージ ステージ 溶融帯 ボンディングパッド 半導体チップ ダイス付は材 ブリーディング ポンディングワイヤ インナーリード パッケージ本体 ステージ 溶融帯 ホンデインクパツド ＩＣチップ タイス付は材 ボンディングワイヤ インナーリード パッケージ益体 インナーリード領域 レーザビーム 溶融領域 く

Claims (5)

    【特許請求の範囲】
  1. （１）セラミック製のパッケージ（１）であって、半導
    体チップを載置するステージ中央部と少なくとも該ステ
    ージの一辺との間のステージ周縁部に表面が溶融された
    溶融帯（３）を有し、溶融帯の外側にインナーリード（
    １０）を有するパッケージ（１）と、 前記パッケージ（１）のステージに樹脂（６）でダイス
    付けされ、表面にボンディングパッド（４）を有する半
    導体チップ（５）と、 前記半導体チップ（５）上のボンディングパッド（４）
    と前記パッケージ上のインナーリード（１０）とを接続
    するボンディングワイヤとを含むセラミックパッケージ
    半導体装置。
  2. （２）前記溶融帯はステージ中央部を囲んでループ状に
    形成されている請求項１記載のセラミックパッケージ半
    導体装置。
  3. （３）前記溶融帯は約１ｍｍ以上の幅を有する請求項１
    または２記載のセラミックパッケージ半導体装置。
  4. （４）セラミックで形成され、半導体チップを搭載する
    ためのステージとその周辺のインナーリード形成領域表
    面上に形成されたインナーリードを有するパッケージの
    ステージ中央部とインナーリードとの間のステージ周縁
    部にレーザビームを照射し、パッケージ表面を溶融して
    の溶融帯を作成する工程と、 ステージ中央部に半導体チップを樹脂でダイス付けする
    工程と、 半導体チップ上のボンディングパッドとインナーリード
    との間をワイヤボンディングする工程と を含むセラミックパッケージ半導体装置の製造方法。
  5. （５）前記溶融帯を作成する工程はレーザビームを走査
    し、幅約１ｍｍ以上の溶融帯を作成することを含む請求
    項４記載のセラミックパッケージ半導体装置の製造方法
    。
JP2129712A 1990-05-18 1990-05-18 セラミックパッケージ半導体装置およびその製造方法 Pending JPH0423441A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2129712A JPH0423441A (ja) 1990-05-18 1990-05-18 セラミックパッケージ半導体装置およびその製造方法
EP91107761A EP0457260A1 (en) 1990-05-18 1991-05-13 Semiconductor device having a ceramic package
US07/700,777 US5091770A (en) 1990-05-18 1991-05-16 Semiconductor device having a ceramic package
KR91007930A KR940008553B1 (en) 1990-05-18 1991-05-16 Semiconductor device having a ceramic package

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EP0457260A1 (en) 1991-11-21
KR910020860A (ko) 1991-12-20
KR940008553B1 (en) 1994-09-24
US5091770A (en) 1992-02-25

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