JPH1197476A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法Info
- Publication number
- JPH1197476A JPH1197476A JP9256994A JP25699497A JPH1197476A JP H1197476 A JPH1197476 A JP H1197476A JP 9256994 A JP9256994 A JP 9256994A JP 25699497 A JP25699497 A JP 25699497A JP H1197476 A JPH1197476 A JP H1197476A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead
- wire
- semiconductor device
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
チップ上のパッドから始まっており、チップ角でのチッ
プとワイヤの接触を回避するために、バッケージサイズ
が小さくならないという欠点があった。 【解決手段】チップ101内のパッド102に予め金ボ
ール103を形成しておき、チップ101の近傍のリー
ド上の点105nからパッド102上の金ボール103
と接着させる方法を採ることにより、ワイヤボンデイン
グの位置をチップ端101bに近づけられるので、バッ
ケージサイズを小さく出来る。
Description
特にCOL(チップ・オン・リード)構造のBGA(ボ
ール・グリッド・アレイ)型CSP(チップ・サイズ・
パッケージ)半導体装置及び半導体装置製造方法に関す
る。
構造のBGA(ボール・グリッド・アレイ)型CSP
(チップ・サイズ・パッケージ)半導体装置は、図3の
断面図に示すように、リード205と、このリード20
5上に搭載されたチップ101と、リード205とチッ
プ101内のパッド102とをパッド102を始点とし
リード205を終点として行われるワイヤボンディング
によって接続するワイヤ204と、チップ101とリー
ド205とワイヤ204とを封止する樹脂207と、リ
ード205にチップ101の裏面側に接着テープ106
で接着される半田ボール108とから成り、全体として
パッケージ209を構成している。
ディングはパッド102から始まっていて、パッド10
2上方では上方部分204uの如くワイヤ204がほぼ
垂直となっているが、ワイヤボンディングの終点205
tに向かうワイヤ部分204gは終点に向かって長くな
だらかな形状となる。
のCOL構造のBGA型CSP半導体装置ではバッケー
ジサイズが小さくならないということである。従来の構
造においては、ワイヤボンディング工程においてワイヤ
ボンディングをチップ101内のパッド102からリー
ド205に向かつて行うが、ワイヤ204はパッド20
2の上方部分204uではほぼ垂直になるが、リード2
05上のワイヤボンディング終点205tに向かう部分
のワイヤ形状204gはなだらかで長い形状にならざる
を得ず、チップ端101bからリード端205bまでの
距離が長くなり、結果的にパッケージサイズが大きくな
ってしまっていた。
BGA型半導体装置を提供することにある。
チップ近傍のリード上の点を起点とし、チップのパッド
を終点として、前記リードと前記パッドとをワイヤによ
り接続し、前記チップ、前記ワイヤ、前記リードを樹脂
被覆し、前記リードを前記樹脂の長さに切断し、前記チ
ップの裏面に位置するよう前記リード上の一部に半田ボ
ールを形成したことを特徴とする。
(a)、(b)及び図2(a)〜(d)を参照して説明
する。図1(a)は本発明の平面図を示し、リード10
5はチップ101の下に複数本敷設されている。図1
(b)は図1(a)のXX線での断面図を示し、リード
105の下方には半田ボール108が接着されている。
チップ101は接着テープ106によりリード105に
接着されている。パッド102には金ボール103が接
着されており、リード105上のワイヤボンディング始
点105nからワイヤ104がワイヤボンディングによ
り金ボール103に接着されている。チップ101、ワ
イヤ104、リード105を含む主要部分は樹脂107
により被覆成形され、パッケージ109を形成してい
る。
法を示す断面図である。まず,図2(a)に示すよう
に、キャピラリ110の中を通してワイヤ104がパッ
ド102に通常のワイヤボンディングにより圧着され
る。次に、図2(b)に示すように金ボール103を残
してワイヤ104を切断し、パッド102の上に金ボー
ル103を形成する。この後、図2(c)のように、チ
ップ101の端101bから90μm〜150μmに位
置するリード105上の点105nを起点として、そこ
から垂直にワイヤボンディングを行い、図2(d)のよ
うにパッド102の上の金ボール103に接着する。
うに、ワイヤがチップ内のパッドからワイヤボンディン
グされるために、ワイヤがチップ角101eに接触しな
いように、パッド202のすぐ上ではワイヤがほぼ垂直
の形状に形成され、ワイヤの終点に向かって長くなだら
かなカーブを描くよう形成される必要があり、リード上
のワイヤボンディングの終点を、チップの端から遠く離
して(チップの端から600μm以上)設定しなければな
らない。このために、リードの終端が、チップの端から
ワイヤの長さに合わせて遠くなる必要と、樹脂で被覆す
べき領域、即ち、パッケージの長さがリード方向に長く
なる必要があった。
(b)のように、ワイヤをチップの端から90μm〜1
50μmと、チップの端に近接したリード上の点から垂
直にワイヤボンディングできるためにリードの長さをリ
ード端105bまでと、短くすることができ、パッケー
ジの大きさを小さくすることができる。
れば、ボンディングワイヤをチップの端部に近接して配
置でき、また、チップの端に近接したリード上の点から
垂直にワイヤボンディングできるためにリードの長さを
短くすることができ、パッケージの大きさを小さくする
ことができる、という効果がある。
置の半田ボール形成直後の平面図及びそのXX線におけ
る断面図である。
工程順に示す断面図である。
A型CSP半導体装置の断面図である。
イヤ形状 204u パッド直上のワイヤ 105、205 リード 105n チップ端に近接するリード上のワイヤボン
ディング始点 105b、205b リード端 205t リード上のワイヤボンディング終点 106 接着テープ 107、207 樹脂 108 半田ボール 109、209 パッケージ 110 キャピラリ
Claims (6)
- 【請求項1】 チップ・オン・リード構造のボール・グ
リッド・アレイ型半導体装置において、チップ近傍のリ
ード上の点を起点とし、そのチップ上のパッドを終点と
して、前記リードと前記パッドとをワイヤにより接続
し、前記チップ、前記ワイヤ、前記リードを樹脂被覆
し、前記リードを前記樹脂の長さに切断し、前記チップ
の裏面に位置するよう前記リード上の一部に半田ボール
を形成したことを特徴とする半導体装置。 - 【請求項2】 前記起点が前記チップの端から90μm
〜150μm離れた前記リード上に位置する請求項1記
載の半導体装置。 - 【請求項3】 前記ワイヤが前記起点から上に向かっ
て、少なくとも前記チップの表面の高さに達するまで、
ほぼ垂直に引き出されている請求項1記載の半導体装
置。 - 【請求項4】 前記パッドの上にはあらかじめワイヤボ
ンディングによる金ボ―ルが接着された請求項1記載の
半導体装置。 - 【請求項5】 チップ・オン・リード構造のボール・グ
リッド・アレイ型半導体装置の製造方法において、パッ
ド上にワイヤボンディングによる金ボールを残留させる
工程、チップ近傍のリード上の点を起点とし、前記パッ
ド上の前記金ボールを終点として、リードとパッドとを
ワイヤボンディングする工程、当該ワイヤボンディング
によるワイヤ、当該チップ、当該リードを被覆すべく樹
脂封止する工程、前記リードを樹脂封止された部分まで
残すよう切断する工程、とからなることを特徴とする半
導体装置の製造方法。 - 【請求項6】 前記ワイヤボンディングによるワイヤ
が、前記リード上の起点から上方に向かって少なくとも
前記チップの高さまで、ほぼ垂直に形成される請求項5
記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9256994A JP2954109B2 (ja) | 1997-09-22 | 1997-09-22 | 半導体装置及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9256994A JP2954109B2 (ja) | 1997-09-22 | 1997-09-22 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1197476A true JPH1197476A (ja) | 1999-04-09 |
JP2954109B2 JP2954109B2 (ja) | 1999-09-27 |
Family
ID=17300251
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9256994A Expired - Fee Related JP2954109B2 (ja) | 1997-09-22 | 1997-09-22 | 半導体装置及びその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2954109B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007023852A1 (ja) * | 2005-08-24 | 2007-03-01 | Fujitsu Limited | 半導体装置及びその製造方法 |
US7417324B2 (en) | 2004-03-10 | 2008-08-26 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
-
1997
- 1997-09-22 JP JP9256994A patent/JP2954109B2/ja not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7417324B2 (en) | 2004-03-10 | 2008-08-26 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
WO2007023852A1 (ja) * | 2005-08-24 | 2007-03-01 | Fujitsu Limited | 半導体装置及びその製造方法 |
JP4998268B2 (ja) * | 2005-08-24 | 2012-08-15 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8841776B2 (en) | 2005-08-24 | 2014-09-23 | Fujitsu Semiconductor Limited | Stacked semiconductor chips having double adhesive insulating layer interposed therebetween |
Also Published As
Publication number | Publication date |
---|---|
JP2954109B2 (ja) | 1999-09-27 |
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