JPH0142346Y2 - - Google Patents

Info

Publication number
JPH0142346Y2
JPH0142346Y2 JP1983190689U JP19068983U JPH0142346Y2 JP H0142346 Y2 JPH0142346 Y2 JP H0142346Y2 JP 1983190689 U JP1983190689 U JP 1983190689U JP 19068983 U JP19068983 U JP 19068983U JP H0142346 Y2 JPH0142346 Y2 JP H0142346Y2
Authority
JP
Japan
Prior art keywords
wire
pellet
bonding pad
semiconductor device
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983190689U
Other languages
English (en)
Other versions
JPS6099536U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1983190689U priority Critical patent/JPS6099536U/ja
Publication of JPS6099536U publication Critical patent/JPS6099536U/ja
Application granted granted Critical
Publication of JPH0142346Y2 publication Critical patent/JPH0142346Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905Shape
    • H01L2224/49051Connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49431Connecting portions the connecting portions being staggered on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 (イ) 産業上の利用分野 本考案は、半導体装置に係り、特に、ペレツト
上に形成されたボンデイングパツドと所定の端子
とを、ワイヤで接続した半導体装置に関する。
(ロ) 従来技術 通常、ボンデイングパツドはペレツト端辺に形
成されている。しかし、半導体装置の集積化を図
る為等によりペレツト表面積を小さくした場合、
パターンレイアウトの関係上、一部のボンデイン
グパツドをペレツト端辺にまで導出できないこと
がある。そのため、ペレツト端辺から遠くのボン
デイングパツドと端子とを接続するワイヤが長く
なる結果、後述するような下具合を生じている。
第1図は前記従来の半導体装置の一部斜視図で
ある。第2図は第1図のワイヤのループ状態を示
した説明図である。
第1図及び第2図において、100は表面にア
イランド120及び端子130が厚膜形成された
セラミツク基板である。110はアイランド12
0上に固着されたペレツトである。このペレツト
110には、端辺側に近いボンデイングパツド1
11と、端辺側から離れたボンデイングパツド1
12が形成されている。このボンデイングパツド
111及び112と端子130との間は同じ太さ
のワイヤ140及び150で接続されている。
第2図aで示すように、短いワイヤ140は撓
んだり、変形することはない、しかし、第2図
b,cで示すように、長いワイヤ150は撓み易
く、ペレツト110の端辺に接触したり、あるい
は、変形して隣り合う短いワイヤ140と接触す
る場合等がある。そのためシヨート不良等を発生
し、半導体装置の歩留りや信頼性を下げる原因と
なる。
(ハ) 目的 本考案は、ワイヤの変形及び撓みによるシヨー
ト不良を防止する半導体装置を提供することを目
的としている。
(ニ) 構成 本考案に係る半導体装置は、ペレツト端辺に近
いボンデイングパツドと所定の端子とを細いワイ
ヤで、又ペレツト端辺から遠いボンデイングパツ
ドと所定の端子とを太いワイヤでそれぞれ接続し
たことを特徴としている。
(ホ) 実施例 第3図は第1図と対応した本考案装置の一実施
例を示す一部斜視図である。第4図は第3図の太
いワイヤのループ状態を、従来の細いワイヤのル
ープ状態との比較で示した断面図である。
第3図、第4図において、第1図と同一部分は
同一符号で示している。
120,130はセラミツク基板100上に厚
膜形成された導電膜よりなるアイランド及び複数
個の端子である。アイランド120の上部に導電
性エポキシ樹脂よりなるプリフオーム材を介して
ペレツト110がダイボンデイングされている。
ボンデイングパツド111は、ペレツト110の
端辺寄りに形成されている。ボンデイングパツド
112は、ペレツト110の端辺から遠くに、し
かもボンデイングパツド111よりも大きく形成
される。
該端子130とボンデイングパツド111は細
い金線140でワイヤボンデイングされている。
又、別の端子130とボンデイングパツド112
は太い金線160でワイヤボンデイングされてい
る。
第4図に示すように、太いワイヤ160は、破
線で示した細いワイヤ150と比較して、撓み及
び変形等が発生しにくい。
尚、アイランド等を厚膜形成したセヤミツク基
板を用いた半導体装置を例にとつて説明したが、
本考案はこれに限定されず、例えば、リードフレ
ーム等を用いるものであつてもよい。
(ヘ) 効果 本考案は、ペレツト端辺から遠いボンデイング
パツドと端子とを太いワイヤで接続させたので、
ワイヤの撓み及び変形を防止できる。
従つて、本考案によれば、シヨート不良を防止
できるので、半導体装置の集積化を図り得るとと
もに歩留り及び信頼性の向上を図ることができ
る。
【図面の簡単な説明】
第1図は従来の半導体装置の一部斜視図、第2
図は第1図のワイヤのループ状態を示した説明
図、第3図は第1図と対応した本考案装置の一実
施例を示す一部斜視図、第4図は第3図の太いワ
イヤのループ状態を、細いワイヤのループ状態と
の比較で示した断面図である。 110……ペレツト、111,112……ボン
デイングパツド、130……端子、140……細
いワイヤ、160……太いワイヤ。

Claims (1)

    【実用新案登録請求の範囲】
  1. ペレツト端辺に近いボンデイングパツドと所定
    の端子とを細いワイヤで、又ペレツト端辺から遠
    いボンデイングパツドと所定の端子とを太いワイ
    ヤで、それぞれ接続したことを特徴とする半導体
    装置。
JP1983190689U 1983-12-10 1983-12-10 半導体装置 Granted JPS6099536U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983190689U JPS6099536U (ja) 1983-12-10 1983-12-10 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983190689U JPS6099536U (ja) 1983-12-10 1983-12-10 半導体装置

Publications (2)

Publication Number Publication Date
JPS6099536U JPS6099536U (ja) 1985-07-06
JPH0142346Y2 true JPH0142346Y2 (ja) 1989-12-12

Family

ID=30410812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983190689U Granted JPS6099536U (ja) 1983-12-10 1983-12-10 半導体装置

Country Status (1)

Country Link
JP (1) JPS6099536U (ja)

Also Published As

Publication number Publication date
JPS6099536U (ja) 1985-07-06

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