JP4130811B2 - 試験装置及び試験方法 - Google Patents

試験装置及び試験方法 Download PDF

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Publication number
JP4130811B2
JP4130811B2 JP2004087924A JP2004087924A JP4130811B2 JP 4130811 B2 JP4130811 B2 JP 4130811B2 JP 2004087924 A JP2004087924 A JP 2004087924A JP 2004087924 A JP2004087924 A JP 2004087924A JP 4130811 B2 JP4130811 B2 JP 4130811B2
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JP
Japan
Prior art keywords
under test
memories
memory
fail
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004087924A
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English (en)
Japanese (ja)
Other versions
JP2005276317A (ja
JP2005276317A5 (enExample
Inventor
益弘 山田
和彦 佐藤
俊美 大沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2004087924A priority Critical patent/JP4130811B2/ja
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to PCT/JP2005/005171 priority patent/WO2005091305A1/ja
Priority to CNB2005800091974A priority patent/CN100524538C/zh
Priority to KR1020067021895A priority patent/KR100838864B1/ko
Priority to DE112005000640T priority patent/DE112005000640T5/de
Priority to TW094109065A priority patent/TWI371594B/zh
Publication of JP2005276317A publication Critical patent/JP2005276317A/ja
Priority to US11/515,350 priority patent/US7441166B2/en
Publication of JP2005276317A5 publication Critical patent/JP2005276317A5/ja
Application granted granted Critical
Publication of JP4130811B2 publication Critical patent/JP4130811B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2004087924A 2004-03-24 2004-03-24 試験装置及び試験方法 Expired - Fee Related JP4130811B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2004087924A JP4130811B2 (ja) 2004-03-24 2004-03-24 試験装置及び試験方法
CNB2005800091974A CN100524538C (zh) 2004-03-24 2005-03-22 测试装置与测试方法
KR1020067021895A KR100838864B1 (ko) 2004-03-24 2005-03-22 시험 장치 및 시험 방법
DE112005000640T DE112005000640T5 (de) 2004-03-24 2005-03-22 Testgerät und Testverfahren
PCT/JP2005/005171 WO2005091305A1 (ja) 2004-03-24 2005-03-22 試験装置及び試験方法
TW094109065A TWI371594B (en) 2004-03-24 2005-03-24 Testing device and testing method
US11/515,350 US7441166B2 (en) 2004-03-24 2006-09-01 Testing apparatus and testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004087924A JP4130811B2 (ja) 2004-03-24 2004-03-24 試験装置及び試験方法

Publications (3)

Publication Number Publication Date
JP2005276317A JP2005276317A (ja) 2005-10-06
JP2005276317A5 JP2005276317A5 (enExample) 2007-07-05
JP4130811B2 true JP4130811B2 (ja) 2008-08-06

Family

ID=34993950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004087924A Expired - Fee Related JP4130811B2 (ja) 2004-03-24 2004-03-24 試験装置及び試験方法

Country Status (7)

Country Link
US (1) US7441166B2 (enExample)
JP (1) JP4130811B2 (enExample)
KR (1) KR100838864B1 (enExample)
CN (1) CN100524538C (enExample)
DE (1) DE112005000640T5 (enExample)
TW (1) TWI371594B (enExample)
WO (1) WO2005091305A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4401319B2 (ja) * 2005-04-07 2010-01-20 株式会社日立製作所 Ｄｒａｍ積層パッケージ並びにｄｒａｍ積層パッケージの試験および救済方法
JP2007322141A (ja) * 2006-05-30 2007-12-13 Yokogawa Electric Corp 半導体集積回路試験装置及び方法
JP5003941B2 (ja) * 2007-02-05 2012-08-22 横河電機株式会社 Ｉｃ試験装置およびｉｃ試験方法
JP5080501B2 (ja) * 2007-02-16 2012-11-21 株式会社アドバンテスト 試験装置および試験方法
US8368418B2 (en) * 2007-11-14 2013-02-05 Advantest Corporation Testing apparatus for multiple identical circuit components
TW200947450A (en) * 2008-05-09 2009-11-16 A Data Technology Co Ltd Storage system capable of data recovery and method thereof
JP5077265B2 (ja) * 2009-02-26 2012-11-21 横河電機株式会社 記憶装置及び半導体試験装置
US8706439B2 (en) * 2009-12-27 2014-04-22 Advantest Corporation Test apparatus and test method
JP2012174313A (ja) 2011-02-23 2012-09-10 Advantest Corp 試験装置
CN104090846A (zh) * 2013-04-01 2014-10-08 深圳芯力电子技术有限公司 一种电子信息产品数据存取方法及电子信息产品
US9251915B2 (en) * 2013-11-11 2016-02-02 Advantest Corporation Seamless fail analysis with memory efficient storage of fail lists
KR102825124B1 (ko) * 2022-12-29 2025-06-25 주식회사 와이씨 인터리브 방식을 이용한 메모리 스크램블 방법 및 장치
KR102835344B1 (ko) * 2022-12-29 2025-07-18 주식회사 와이씨 메모리 페일 카운트 방법 및 시스템

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100192064B1 (ko) * 1990-04-17 1999-06-15 가나이 쓰도무 저저항 배선구조를 갖는 반도체장치 및 그 제조방법
US5070297A (en) * 1990-06-04 1991-12-03 Texas Instruments Incorporated Full wafer integrated circuit testing device
US5610925A (en) * 1995-03-27 1997-03-11 Advantest Corporation Failure analyzer for semiconductor tester
JPH0933615A (ja) * 1995-07-19 1997-02-07 Advantest Corp 半導体メモリ試験装置のメモリ不良解析装置
US5790559A (en) * 1996-03-29 1998-08-04 Advantest Corporation Semiconductor memory testing apparatus
US6499121B1 (en) * 1999-03-01 2002-12-24 Formfactor, Inc. Distributed interface for parallel testing of multiple devices using a single tester channel
WO2002033708A1 (en) * 2000-10-19 2002-04-25 Advantest Corporation Memory defect redress analysis treating method, and memory testing apparatus performing the method
JP4377238B2 (ja) * 2001-11-15 2009-12-02 株式会社アドバンテスト 半導体試験装置
JP4097069B2 (ja) 2002-08-28 2008-06-04 Ｔｄｋ株式会社 プリント基板の製造方法
US7036053B2 (en) * 2002-12-19 2006-04-25 Intel Corporation Two dimensional data eye centering for source synchronous data transfers
JP4308637B2 (ja) * 2003-12-17 2009-08-05 株式会社日立製作所 半導体試験装置
US20070061669A1 (en) * 2005-08-30 2007-03-15 Major Karl L Method, device and system for detecting error correction defects

Also Published As

Publication number Publication date
JP2005276317A (ja) 2005-10-06
US20070067685A1 (en) 2007-03-22
TWI371594B (en) 2012-09-01
KR100838864B1 (ko) 2008-06-16
DE112005000640T5 (de) 2008-07-03
US7441166B2 (en) 2008-10-21
CN1934654A (zh) 2007-03-21
WO2005091305A1 (ja) 2005-09-29
TW200533943A (en) 2005-10-16
KR20060135036A (ko) 2006-12-28
CN100524538C (zh) 2009-08-05

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