JP4106811B2 - 半導体記憶装置及び電子装置 - Google Patents

半導体記憶装置及び電子装置 Download PDF

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Publication number
JP4106811B2
JP4106811B2 JP16346199A JP16346199A JP4106811B2 JP 4106811 B2 JP4106811 B2 JP 4106811B2 JP 16346199 A JP16346199 A JP 16346199A JP 16346199 A JP16346199 A JP 16346199A JP 4106811 B2 JP4106811 B2 JP 4106811B2
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Japan
Prior art keywords
refresh
signal
output
semiconductor memory
memory device
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Expired - Fee Related
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JP16346199A
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English (en)
Japanese (ja)
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JP2000353382A5 (cg-RX-API-DMAC7.html
JP2000353382A (ja
Inventor
明裕 舩生
伸也 藤岡
仁史 池田
孝章 鈴木
眞男 田口
公昭 佐藤
光徳 佐藤
康郎 松崎
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP16346199A priority Critical patent/JP4106811B2/ja
Priority to US09/536,988 priority patent/US6535950B1/en
Priority to DE60043326T priority patent/DE60043326D1/de
Priority to EP00302717A priority patent/EP1061523B1/en
Priority to TW089107437A priority patent/TW468184B/zh
Priority to KR1020000020942A priority patent/KR100607918B1/ko
Publication of JP2000353382A publication Critical patent/JP2000353382A/ja
Priority to US10/352,985 priority patent/US6724675B2/en
Publication of JP2000353382A5 publication Critical patent/JP2000353382A5/ja
Priority to KR1020060037623A priority patent/KR100609677B1/ko
Application granted granted Critical
Publication of JP4106811B2 publication Critical patent/JP4106811B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618Refresh operations over multiple banks or interleaving
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072Circuits for initialization, powering up or down, clearing memory or presetting
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063Control signal output circuits, e.g. status or busy flags, feedback command signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109Control signal input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/04Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP16346199A 1999-06-10 1999-06-10 半導体記憶装置及び電子装置 Expired - Fee Related JP4106811B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP16346199A JP4106811B2 (ja) 1999-06-10 1999-06-10 半導体記憶装置及び電子装置
US09/536,988 US6535950B1 (en) 1999-06-10 2000-03-29 Semiconductor memory device having a refresh operation
EP00302717A EP1061523B1 (en) 1999-06-10 2000-03-31 Semiconductor memory device and electronic apparatus
DE60043326T DE60043326D1 (de) 1999-06-10 2000-03-31 Halbleiterspeicheranordnung und elektronisches Gerät
TW089107437A TW468184B (en) 1999-06-10 2000-04-20 Semiconductor memory device and electronic apparatus
KR1020000020942A KR100607918B1 (ko) 1999-06-10 2000-04-20 반도체 기억 장치 및 전자 장치
US10/352,985 US6724675B2 (en) 1999-06-10 2003-01-29 Semiconductor memory device and electronic apparatus
KR1020060037623A KR100609677B1 (ko) 1999-06-10 2006-04-26 반도체 기억 장치 및 전자 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16346199A JP4106811B2 (ja) 1999-06-10 1999-06-10 半導体記憶装置及び電子装置

Publications (3)

Publication Number Publication Date
JP2000353382A JP2000353382A (ja) 2000-12-19
JP2000353382A5 JP2000353382A5 (cg-RX-API-DMAC7.html) 2004-12-09
JP4106811B2 true JP4106811B2 (ja) 2008-06-25

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Country Link
US (2) US6535950B1 (cg-RX-API-DMAC7.html)
EP (1) EP1061523B1 (cg-RX-API-DMAC7.html)
JP (1) JP4106811B2 (cg-RX-API-DMAC7.html)
KR (2) KR100607918B1 (cg-RX-API-DMAC7.html)
DE (1) DE60043326D1 (cg-RX-API-DMAC7.html)
TW (1) TW468184B (cg-RX-API-DMAC7.html)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3624849B2 (ja) 2001-04-02 2005-03-02 セイコーエプソン株式会社 半導体装置、そのリフレッシュ方法、メモリシステムおよび電子機器
JP4712214B2 (ja) * 2001-04-09 2011-06-29 富士通セミコンダクター株式会社 半導体メモリの動作制御方法および半導体メモリ
JP2003228511A (ja) * 2002-02-04 2003-08-15 Elpida Memory Inc データ書込方法及びメモリシステム
US7043599B1 (en) * 2002-06-20 2006-05-09 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
KR100455393B1 (ko) * 2002-08-12 2004-11-06 삼성전자주식회사 리프레시 플래그를 발생시키는 반도체 메모리 장치 및반도체 메모리 시스템.
WO2004027780A1 (ja) 2002-09-20 2004-04-01 Fujitsu Limited 半導体メモリ
JP4996094B2 (ja) * 2003-10-24 2012-08-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置及びそのリフレッシュ方法
KR20060009446A (ko) * 2004-07-22 2006-02-01 삼성전자주식회사 프로세서의 오동작을 방지할 수 있는 정보 처리 장치
JP4562468B2 (ja) * 2004-09-13 2010-10-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100574989B1 (ko) * 2004-11-04 2006-05-02 삼성전자주식회사 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법
JPWO2006080065A1 (ja) 2005-01-27 2008-06-19 スパンション エルエルシー 記憶装置、およびその制御方法
JP4756581B2 (ja) * 2005-07-21 2011-08-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
US20070073874A1 (en) * 2005-09-07 2007-03-29 Ace Comm Consumer configurable mobile communication solution
JP2007115087A (ja) * 2005-10-21 2007-05-10 Oki Electric Ind Co Ltd 半導体装置
WO2008127458A2 (en) 2006-12-06 2008-10-23 Fusion Multisystems, Inc. (Dba Fusion-Io) Apparatus, system, and method for a shared, front-end, distributed raid
US7797511B2 (en) * 2007-01-05 2010-09-14 Qimonda North America Corp. Memory refresh system and method
US8767450B2 (en) * 2007-08-21 2014-07-01 Samsung Electronics Co., Ltd. Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same
KR20100134375A (ko) * 2009-06-15 2010-12-23 삼성전자주식회사 리프레쉬 동작을 수행하는 메모리 시스템
US7836226B2 (en) 2007-12-06 2010-11-16 Fusion-Io, Inc. Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US8064250B2 (en) * 2008-12-16 2011-11-22 Micron Technology, Inc. Providing a ready-busy signal from a non-volatile memory device to a memory controller
KR20110111551A (ko) * 2008-12-30 2011-10-12 에마누엘르 콘파로니에리 동작 온도 범위가 확장된 비휘발성 메모리
US9223514B2 (en) 2009-09-09 2015-12-29 SanDisk Technologies, Inc. Erase suspend/resume for memory
US8429436B2 (en) 2009-09-09 2013-04-23 Fusion-Io, Inc. Apparatus, system, and method for power reduction in a storage device
US9021158B2 (en) 2009-09-09 2015-04-28 SanDisk Technologies, Inc. Program suspend/resume for memory
US8984216B2 (en) 2010-09-09 2015-03-17 Fusion-Io, Llc Apparatus, system, and method for managing lifetime of a storage device
US9208071B2 (en) 2010-12-13 2015-12-08 SanDisk Technologies, Inc. Apparatus, system, and method for accessing memory
US10817502B2 (en) 2010-12-13 2020-10-27 Sandisk Technologies Llc Persistent memory management
US9218278B2 (en) 2010-12-13 2015-12-22 SanDisk Technologies, Inc. Auto-commit memory
US10817421B2 (en) 2010-12-13 2020-10-27 Sandisk Technologies Llc Persistent data structures
WO2012109677A2 (en) * 2011-02-11 2012-08-16 Fusion-Io, Inc. Apparatus, system, and method for managing operations for data storage media
US9911485B2 (en) * 2013-11-11 2018-03-06 Qualcomm Incorporated Method and apparatus for refreshing a memory cell
US9666244B2 (en) 2014-03-01 2017-05-30 Fusion-Io, Inc. Dividing a storage procedure
KR20160063726A (ko) * 2014-11-27 2016-06-07 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
US9933950B2 (en) 2015-01-16 2018-04-03 Sandisk Technologies Llc Storage operation interrupt
KR102384962B1 (ko) * 2015-11-27 2022-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치
DE102017106713B4 (de) 2016-04-20 2025-10-02 Samsung Electronics Co., Ltd. Rechensystem, nichtflüchtiges Speichermodul und Verfahren zum Betreiben einer Speichervorrichtung
US10490251B2 (en) 2017-01-30 2019-11-26 Micron Technology, Inc. Apparatuses and methods for distributing row hammer refresh events across a memory device
CN112106138B (zh) 2018-05-24 2024-02-27 美光科技公司 用于行锤击刷新采样的纯时间自适应采样的设备和方法
US10685696B2 (en) 2018-10-31 2020-06-16 Micron Technology, Inc. Apparatuses and methods for access based refresh timing
WO2020117686A1 (en) 2018-12-03 2020-06-11 Micron Technology, Inc. Semiconductor device performing row hammer refresh operation
CN117198356A (zh) 2018-12-21 2023-12-08 美光科技公司 用于目标刷新操作的时序交错的设备和方法
US10957377B2 (en) 2018-12-26 2021-03-23 Micron Technology, Inc. Apparatuses and methods for distributed targeted refresh operations
JP6894459B2 (ja) * 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. 疑似スタティックランダムアクセスメモリとその動作方法
US11615831B2 (en) 2019-02-26 2023-03-28 Micron Technology, Inc. Apparatuses and methods for memory mat refresh sequencing
US11227649B2 (en) 2019-04-04 2022-01-18 Micron Technology, Inc. Apparatuses and methods for staggered timing of targeted refresh operations
US11069393B2 (en) 2019-06-04 2021-07-20 Micron Technology, Inc. Apparatuses and methods for controlling steal rates
US10978132B2 (en) 2019-06-05 2021-04-13 Micron Technology, Inc. Apparatuses and methods for staggered timing of skipped refresh operations
US11302374B2 (en) 2019-08-23 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic refresh allocation
US11302377B2 (en) 2019-10-16 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic targeted refresh steals
US11309010B2 (en) * 2020-08-14 2022-04-19 Micron Technology, Inc. Apparatuses, systems, and methods for memory directed access pause
US11380382B2 (en) 2020-08-19 2022-07-05 Micron Technology, Inc. Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
US11348631B2 (en) 2020-08-19 2022-05-31 Micron Technology, Inc. Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
US11430504B2 (en) * 2020-08-27 2022-08-30 Micron Technology, Inc. Row clear features for memory devices and associated methods and systems
US11557331B2 (en) 2020-09-23 2023-01-17 Micron Technology, Inc. Apparatuses and methods for controlling refresh operations
US11222686B1 (en) 2020-11-12 2022-01-11 Micron Technology, Inc. Apparatuses and methods for controlling refresh timing
US11264079B1 (en) 2020-12-18 2022-03-01 Micron Technology, Inc. Apparatuses and methods for row hammer based cache lockdown
US11972788B2 (en) * 2021-03-11 2024-04-30 Micron Technology, Inc. Apparatuses, systems, and methods for controller directed targeted refresh operations based on sampling command
US12125514B2 (en) 2022-04-28 2024-10-22 Micron Technology, Inc. Apparatuses and methods for access based refresh operations
US12112787B2 (en) 2022-04-28 2024-10-08 Micron Technology, Inc. Apparatuses and methods for access based targeted refresh operations
US12436854B2 (en) * 2023-09-20 2025-10-07 Nanya Technology Corporation Memory device and control method for performing row hammer protection

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4145739A (en) * 1977-06-20 1979-03-20 Wang Laboratories, Inc. Distributed data processing system
JPS6079593A (ja) 1983-10-07 1985-05-07 Hitachi Ltd 半導体集積回路システム
US4639890A (en) * 1983-12-30 1987-01-27 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers
US4758993A (en) 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4829467A (en) 1984-12-21 1989-05-09 Canon Kabushiki Kaisha Memory controller including a priority order determination circuit
US4691303A (en) 1985-10-31 1987-09-01 Sperry Corporation Refresh system for multi-bank semiconductor memory
JPH07107793B2 (ja) 1987-11-10 1995-11-15 株式会社東芝 仮想型スタティック半導体記憶装置及びこの記憶装置を用いたシステム
FR2644260B1 (fr) 1989-03-08 1993-10-29 Nec Corp Dispositif de commande d'acces en memoire pouvant proceder a une commande simple
JP2827361B2 (ja) 1989-12-04 1998-11-25 日本電気株式会社 半導体メモリ装置
US5289413A (en) * 1990-06-08 1994-02-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device with high-speed serial-accessing column decoder
EP0895162A3 (en) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Enhanced dram with embedded registers
GB2265035B (en) 1992-03-12 1995-11-22 Apple Computer Method and apparatus for improved dram refresh operations
US5519839A (en) 1992-10-02 1996-05-21 Compaq Computer Corp. Double buffering operations between the memory bus and the expansion bus of a computer system
US5617367A (en) * 1993-09-01 1997-04-01 Micron Technology, Inc. Controlling synchronous serial access to a multiport memory
KR970008412B1 (ko) * 1993-10-15 1997-05-23 엘지반도체 주식회사 디지탈 영상신호 처리용 메모리 시스템
KR0171930B1 (ko) * 1993-12-15 1999-03-30 모리시다 요이치 반도체 메모리, 동화기억 메모리, 동화기억장치, 동화표시장치, 정지화기억 메모리 및 전자노트
US5634073A (en) 1994-10-14 1997-05-27 Compaq Computer Corporation System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
JPH08129882A (ja) 1994-10-31 1996-05-21 Mitsubishi Electric Corp 半導体記憶装置
US5796671A (en) * 1996-03-01 1998-08-18 Wahlstrom; Sven E. Dynamic random access memory
FR2749681B1 (fr) 1996-06-10 1998-07-10 Bull Sa Circuit pour transborder des donnees entre memoires distantes et calculateur comprenant un tel circuit
JPH10247384A (ja) 1997-03-03 1998-09-14 Mitsubishi Electric Corp 同期型半導体記憶装置
US6396744B1 (en) * 2000-04-25 2002-05-28 Multi Level Memory Technology Flash memory with dynamic refresh
US6515914B2 (en) * 2001-03-21 2003-02-04 Micron Technology, Inc. Memory device and method having data path with multiple prefetch I/O configurations

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US20030115405A1 (en) 2003-06-19
EP1061523A1 (en) 2000-12-20
KR100609677B1 (ko) 2006-08-08
KR100607918B1 (ko) 2006-08-04
US6535950B1 (en) 2003-03-18
KR20060080559A (ko) 2006-07-10
KR20010006998A (ko) 2001-01-26
JP2000353382A (ja) 2000-12-19
US6724675B2 (en) 2004-04-20
TW468184B (en) 2001-12-11
EP1061523B1 (en) 2009-11-18
DE60043326D1 (de) 2009-12-31

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