JP3929116B2 - メモリサブシステム - Google Patents

メモリサブシステム Download PDF

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Publication number
JP3929116B2
JP3929116B2 JP17996997A JP17996997A JP3929116B2 JP 3929116 B2 JP3929116 B2 JP 3929116B2 JP 17996997 A JP17996997 A JP 17996997A JP 17996997 A JP17996997 A JP 17996997A JP 3929116 B2 JP3929116 B2 JP 3929116B2
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JP
Japan
Prior art keywords
clock
data
controller
memory
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17996997A
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English (en)
Japanese (ja)
Other versions
JPH1125029A5 (enExample
JPH1125029A (ja
Inventor
正夫 中野
浩由 富田
光徳 佐藤
寿博 竹前
眞男 田口
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Fujitsu Ltd
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Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17996997A priority Critical patent/JP3929116B2/ja
Priority to TW086116931A priority patent/TW351787B/zh
Priority to US08/970,086 priority patent/US6397312B1/en
Priority to KR1019970063317A priority patent/KR100271724B1/ko
Publication of JPH1125029A publication Critical patent/JPH1125029A/ja
Publication of JPH1125029A5 publication Critical patent/JPH1125029A5/ja
Application granted granted Critical
Publication of JP3929116B2 publication Critical patent/JP3929116B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
JP17996997A 1997-07-04 1997-07-04 メモリサブシステム Expired - Fee Related JP3929116B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP17996997A JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム
TW086116931A TW351787B (en) 1997-07-04 1997-11-13 Memory subsystem capable of high speed data transfer
US08/970,086 US6397312B1 (en) 1997-07-04 1997-11-13 Memory subsystem operated in synchronism with a clock
KR1019970063317A KR100271724B1 (ko) 1997-07-04 1997-11-27 메모리 서브 시스템

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17996997A JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム

Publications (3)

Publication Number Publication Date
JPH1125029A JPH1125029A (ja) 1999-01-29
JPH1125029A5 JPH1125029A5 (enExample) 2004-12-02
JP3929116B2 true JP3929116B2 (ja) 2007-06-13

Family

ID=16075154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17996997A Expired - Fee Related JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム

Country Status (4)

Country Link
US (1) US6397312B1 (enExample)
JP (1) JP3929116B2 (enExample)
KR (1) KR100271724B1 (enExample)
TW (1) TW351787B (enExample)

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JP4785465B2 (ja) * 2005-08-24 2011-10-05 ルネサスエレクトロニクス株式会社 インタフェース回路及び半導体装置
US7269093B2 (en) * 2005-10-31 2007-09-11 Infineon Technologies Ag Generating a sampling clock signal in a communication block of a memory device
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US7666160B2 (en) * 2006-12-29 2010-02-23 Kimberly-Clark Worldwide, Inc. Delivery device
JP4325685B2 (ja) * 2007-02-21 2009-09-02 セイコーエプソン株式会社 メモリを制御するメモリコントローラ、メモリモジュール、メモリの制御方法、および、コンピュータ。
US7586355B2 (en) * 2007-07-11 2009-09-08 United Memories, Inc. Low skew clock distribution tree
CN101373639B (zh) * 2007-08-22 2011-02-09 智原科技股份有限公司 存储器时序测量电路与其测试方法
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CN102946293B (zh) * 2012-09-26 2015-09-23 中国航天科技集团公司第九研究院第七七一研究所 一种基于ds编码的并行接收方法及其装置
US9111607B2 (en) * 2013-05-31 2015-08-18 Freescale Semiconductor, Inc. Multiple data rate memory with read timing information
JP6188246B2 (ja) * 2015-07-10 2017-08-30 株式会社メガチップス メモリシステム
JP6207551B2 (ja) * 2015-07-10 2017-10-04 株式会社メガチップス メモリシステム
CN107977328B (zh) * 2017-12-20 2019-12-10 天津瑞发科半导体技术有限公司 一种onfi接口双时钟沿采样装置

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Also Published As

Publication number Publication date
JPH1125029A (ja) 1999-01-29
TW351787B (en) 1999-02-01
KR19990013250A (ko) 1999-02-25
KR100271724B1 (ko) 2000-11-15
US6397312B1 (en) 2002-05-28

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