KR100271724B1 - 메모리 서브 시스템 - Google Patents

메모리 서브 시스템 Download PDF

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Publication number
KR100271724B1
KR100271724B1 KR1019970063317A KR19970063317A KR100271724B1 KR 100271724 B1 KR100271724 B1 KR 100271724B1 KR 1019970063317 A KR1019970063317 A KR 1019970063317A KR 19970063317 A KR19970063317 A KR 19970063317A KR 100271724 B1 KR100271724 B1 KR 100271724B1
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South Korea
Prior art keywords
data
clock
memory
signal line
controller
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Expired - Fee Related
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KR1019970063317A
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English (en)
Korean (ko)
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KR19990013250A (ko
Inventor
마사오 나카노
히로요시 토미타
마사오 다구치
고토쿠 사토
요시히로 다케마에
Original Assignee
아끼구사 나오유끼
후지쯔 가부시끼가이샤
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Publication of KR19990013250A publication Critical patent/KR19990013250A/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
KR1019970063317A 1997-07-04 1997-11-27 메모리 서브 시스템 Expired - Fee Related KR100271724B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP97-179969 1997-07-04
JP17996997A JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム

Publications (2)

Publication Number Publication Date
KR19990013250A KR19990013250A (ko) 1999-02-25
KR100271724B1 true KR100271724B1 (ko) 2000-11-15

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KR1019970063317A Expired - Fee Related KR100271724B1 (ko) 1997-07-04 1997-11-27 메모리 서브 시스템

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Country Link
US (1) US6397312B1 (enExample)
JP (1) JP3929116B2 (enExample)
KR (1) KR100271724B1 (enExample)
TW (1) TW351787B (enExample)

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KR100562645B1 (ko) * 2004-10-29 2006-03-20 주식회사 하이닉스반도체 반도체 기억 소자
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US7586355B2 (en) * 2007-07-11 2009-09-08 United Memories, Inc. Low skew clock distribution tree
CN101373639B (zh) * 2007-08-22 2011-02-09 智原科技股份有限公司 存储器时序测量电路与其测试方法
JP5537568B2 (ja) 2009-12-25 2014-07-02 富士通株式会社 信号受信回路、メモリコントローラ、プロセッサ、コンピュータ及び位相制御方法
JP5331902B2 (ja) 2009-12-25 2013-10-30 富士通株式会社 信号復元回路、レイテンシ調整回路、メモリコントローラ、プロセッサ、コンピュータ、信号復元方法及びレイテンシ調整方法
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US8683253B2 (en) * 2011-06-21 2014-03-25 Via Technologies, Inc. Optimized synchronous strobe transmission mechanism
CN102946293B (zh) * 2012-09-26 2015-09-23 中国航天科技集团公司第九研究院第七七一研究所 一种基于ds编码的并行接收方法及其装置
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JP6188246B2 (ja) * 2015-07-10 2017-08-30 株式会社メガチップス メモリシステム
CN107977328B (zh) * 2017-12-20 2019-12-10 天津瑞发科半导体技术有限公司 一种onfi接口双时钟沿采样装置

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Also Published As

Publication number Publication date
US6397312B1 (en) 2002-05-28
TW351787B (en) 1999-02-01
JP3929116B2 (ja) 2007-06-13
JPH1125029A (ja) 1999-01-29
KR19990013250A (ko) 1999-02-25

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