JPH1125029A5 - - Google Patents

Info

Publication number
JPH1125029A5
JPH1125029A5 JP1997179969A JP17996997A JPH1125029A5 JP H1125029 A5 JPH1125029 A5 JP H1125029A5 JP 1997179969 A JP1997179969 A JP 1997179969A JP 17996997 A JP17996997 A JP 17996997A JP H1125029 A5 JPH1125029 A5 JP H1125029A5
Authority
JP
Japan
Prior art keywords
clock
data
controller
signal line
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997179969A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1125029A (ja
JP3929116B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP17996997A priority Critical patent/JP3929116B2/ja
Priority claimed from JP17996997A external-priority patent/JP3929116B2/ja
Priority to TW086116931A priority patent/TW351787B/zh
Priority to US08/970,086 priority patent/US6397312B1/en
Priority to KR1019970063317A priority patent/KR100271724B1/ko
Publication of JPH1125029A publication Critical patent/JPH1125029A/ja
Publication of JPH1125029A5 publication Critical patent/JPH1125029A5/ja
Application granted granted Critical
Publication of JP3929116B2 publication Critical patent/JP3929116B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP17996997A 1997-07-04 1997-07-04 メモリサブシステム Expired - Fee Related JP3929116B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP17996997A JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム
TW086116931A TW351787B (en) 1997-07-04 1997-11-13 Memory subsystem capable of high speed data transfer
US08/970,086 US6397312B1 (en) 1997-07-04 1997-11-13 Memory subsystem operated in synchronism with a clock
KR1019970063317A KR100271724B1 (ko) 1997-07-04 1997-11-27 메모리 서브 시스템

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17996997A JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム

Publications (3)

Publication Number Publication Date
JPH1125029A JPH1125029A (ja) 1999-01-29
JPH1125029A5 true JPH1125029A5 (enExample) 2004-12-02
JP3929116B2 JP3929116B2 (ja) 2007-06-13

Family

ID=16075154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17996997A Expired - Fee Related JP3929116B2 (ja) 1997-07-04 1997-07-04 メモリサブシステム

Country Status (4)

Country Link
US (1) US6397312B1 (enExample)
JP (1) JP3929116B2 (enExample)
KR (1) KR100271724B1 (enExample)
TW (1) TW351787B (enExample)

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KR100562645B1 (ko) * 2004-10-29 2006-03-20 주식회사 하이닉스반도체 반도체 기억 소자
JP4785465B2 (ja) * 2005-08-24 2011-10-05 ルネサスエレクトロニクス株式会社 インタフェース回路及び半導体装置
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US7666160B2 (en) * 2006-12-29 2010-02-23 Kimberly-Clark Worldwide, Inc. Delivery device
JP4325685B2 (ja) * 2007-02-21 2009-09-02 セイコーエプソン株式会社 メモリを制御するメモリコントローラ、メモリモジュール、メモリの制御方法、および、コンピュータ。
US7586355B2 (en) * 2007-07-11 2009-09-08 United Memories, Inc. Low skew clock distribution tree
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KR20120096028A (ko) 2009-12-25 2012-08-29 후지쯔 가부시끼가이샤 신호 수신 회로, 메모리 컨트롤러, 프로세서, 컴퓨터 및 위상 제어 방법
EP2518630A4 (en) 2009-12-25 2013-01-23 Fujitsu Ltd SIGNAL DECODER SWITCHING, LATCH SETUP SWITCH, MEMORY CONTROL, PROCESSOR, COMPUTER, SIGNAL DECODING METHOD, AND LATENCE SETTING METHOD
JP5320345B2 (ja) * 2010-06-09 2013-10-23 株式会社村田製作所 配線基板
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US8782459B2 (en) 2011-06-21 2014-07-15 Via Technologies, Inc. Apparatus and method for advanced synchronous strobe transmission
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CN102946293B (zh) * 2012-09-26 2015-09-23 中国航天科技集团公司第九研究院第七七一研究所 一种基于ds编码的并行接收方法及其装置
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JP6188246B2 (ja) * 2015-07-10 2017-08-30 株式会社メガチップス メモリシステム
JP6207551B2 (ja) * 2015-07-10 2017-10-04 株式会社メガチップス メモリシステム
CN107977328B (zh) * 2017-12-20 2019-12-10 天津瑞发科半导体技术有限公司 一种onfi接口双时钟沿采样装置

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