JP3637330B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3637330B2
JP3637330B2 JP2002141495A JP2002141495A JP3637330B2 JP 3637330 B2 JP3637330 B2 JP 3637330B2 JP 2002141495 A JP2002141495 A JP 2002141495A JP 2002141495 A JP2002141495 A JP 2002141495A JP 3637330 B2 JP3637330 B2 JP 3637330B2
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Japan
Prior art keywords
gate
semiconductor device
wiring
source electrode
trench
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Expired - Lifetime
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JP2002141495A
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JP2003332576A (ja
Inventor
宏文 松木
孝弘 河野
彰夫 高野
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Toshiba Corp
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Toshiba Corp
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Priority to JP2002141495A priority Critical patent/JP3637330B2/ja
Priority to US10/438,814 priority patent/US6930355B2/en
Publication of JP2003332576A publication Critical patent/JP2003332576A/ja
Application granted granted Critical
Publication of JP3637330B2 publication Critical patent/JP3637330B2/ja
Priority to US11/140,231 priority patent/US20050247974A1/en
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に係り、特にＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）の表面ソース電極がストラップを介してリードフレームに電気的に接続された半導体装置に関するもので、例えばトレンチゲート型のパワーＭＯＳＦＥＴに使用されるものである。
【０００２】
【従来の技術】
図４は、ワイヤボンディング構造を採用したトレンチゲート型のパワーＭＯＳＦＥＴ（従来例）の一部を概略的に示す平面図であり、図５は図４中のＢ−Ｂ線に沿う構造を概略的に示す断面図である。
【０００３】
このパワーＭＯＳＦＥＴは、ソース拡散層4 に連なる表面ソース電極（Source-AL ）１３およびゲートポリシリコン配線７ａに連なる表面ゲート電極（Gate-AL ）１４を有するＭＯＳＦＥＴ素子が形成された半導体チップ４０がリードフレーム（図示せず）上に搭載されている。そして、前記表面ソース電極１３を前記リードフレームに電気的に接続するようにワイヤ（Source-Wire ）４１がボンディング接続されており、前記表面ゲート電極１４を前記リードフレームのリード部に電気的に接続するようにワイヤ（Gate-Wire ）15がボンディング接続されている。
【０００４】
前記表面ソース電極１３および表面ゲート電極１４はそれぞれＡｌを主成分とするＡｌ電極が用いられている。また、ゲートポリシリコン配線７ａの一部は、ソース拡散層4 の配列内で平面ストライプ状に形成されており、ゲートの素子内部抵抗（以下、ｒｇと記す）を下げる目的でＡｌを主成分とするゲートＡｌ（Gate-Al ）配線４２が前記ゲートポリシリコン配線７ａの上面にコンタクトするように形成されている。この場合、ゲートＡｌ配線４２は表面ソース電極１３に対して平面櫛状に入り組むように形成されている。
【０００５】
一方、近年、パワーＭＯＳＦＥＴの低オン抵抗化が強く要望されており、それを実現するパッケージの一つとして、例えば特開2000-114445 などに代表されるように、表面ソース電極をストラップにより接続するストラップ構造が注目されている。
【０００６】
従来のパワーＭＯＳＦＥＴのストラップ構造は、表面ソース電極上にＡｇペースト等の接着剤を介してＣｕ材のストラップを接続している。
【０００７】
しかし、上記したようなストラップ構造は、パワーＭＯＳＦＥＴに対する温度サイクルテスト等の信頼性試験において、チップ表面のＡｌ電極、Ａｇペースト、Ｃｕストラップ、Ｃｕリードフレームの熱膨張係数がそれぞれ異なるので、パワーＭＯＳＦＥＴの寿命が短くなるという問題を内在する。
【０００８】
この問題を解決するため、超音波（以下、ＵＳと記す）を用いてストラップを接続する方法が提案されている。
【０００９】
図６は、ストラップ構造を採用したパワーＭＯＳＦＥＴ（提案例）の一部を概略的に示す平面図、図７は図６中のＢ−Ｂ線に沿う構造を概略的に示す断面図である。図６および図７において、図４および図５中と同一部分には同一符号を付している。
【００１０】
このパワーＭＯＳＦＥＴのストラップ構造は、表面ソース電極１３上にＣｕ材またはＡｌ材のストラップ（Source-Strup）１６をＵＳ接続することによって、ストラップ構造の信頼性は飛躍的に向上する。
【００１１】
この場合、表面ソース電極１３上にストラップがＵＳ接続されるので、図４に示した従来例と同様にゲートＡｌ配線４２が存在すると、その近傍でストラップがＵＳ接続される時に、ゲートＡｌ配線４２の崩れによりゲートＡｌ配線４２が表面ソース電極１３と短絡し、ゲートＧ−ソースＳ間のショート不良が多発する。
【００１２】
したがって、図６に示すようにゲートＡｌ配線を省略し、表面ソース電極１３に対してゲートＡｌ配線４２が平面櫛状に入り組まないようにしている。
【００１３】
しかし、ゲートＡｌ配線４２の存在はゲートの素子内部抵抗ｒｇに大きく影響し、図６に示す提案例のようにゲートＡｌ配線を省略すると、ｒｇは、従来例のゲートＡｌ配線４２が存在する場合の１．５Ω程度に比べて約２倍（３Ω程度）に上昇する。このｒｇの上昇は、パワーＭＯＳＦＥＴを同期整流の用途に使用しようとする場合に変換効率を低下させるようになるので、同期整流の用途に使用できなくなる。
【００１４】
【発明が解決しようとする課題】
上記したように従来提案されているパワーＭＯＳＦＥＴは、信頼性を向上させるために表面ソース電極上にストラップを超音波接続する場合に、ゲートＡｌ配線を設けることができず、ゲートの素子内部抵抗ｒｇが上昇する原因になるという問題があった。
【００１５】
本発明は上記の問題点を解決すべくなされたもので、半導体素子の表面ソース電極上に接続されるストラップ構造の信頼性を向上させることと、半導体素子のゲートの素子内部抵抗ｒｇを低く維持することを両立させ得る半導体装置を提供することを目的とする。
【００１６】
【課題を解決するための手段】
本発明の半導体装置は、ソース拡散層に連なる表面ソース電極およびゲートポリシリコン配線に連なる表面ゲート電極を有する半導体素子が形成されており、前記ゲートポリシリコン配線の上面の少なくとも一部がシリサイド化されている半導体チップと、前記半導体チップを搭載したリードフレームに前記表面ソース電極を電気的に接続するように超音波を用いて接続されたストラップと、前記半導体素子のゲート電極を前記リードフレームのリード部に電気的に接続する配線とを具備することを特徴とする。
【００１７】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
【００１８】
＜第１の実施形態＞
図１は、本発明の第１の実施形態に係るストラップ構造を採用したトレンチゲート型のパワーＮ（チャネル）ＭＯＳＦＥＴの一部を概略的に示す平面図、図２は図１中のＢ−Ｂ線に沿う構造を概略的に示す断面図である。
【００１９】
図１および図２に示すパワーＭＯＳＦＥＴは、ソース拡散層４に連なる表面ソース電極（Source-AL ）１３およびゲートポリシリコン配線７ａに連なる表面ゲート電極（Gate-AL ）１４を有するＭＯＳＦＥＴ素子が形成された半導体チップ２０がリードフレーム（図示せず）上に搭載されている。
【００２０】
そして、前記表面ゲート電極１４を前記リードフレームのリード部に電気的に接続する配線、本例ではワイヤ（Gate-Wire ）１５がボンディング接続されている。
【００２１】
さらに、表面ソース電極１３を前記リードフレームに電気的に接続するように、表面ソース電極１３上にＣｕ材またはＡｌ材のストラップ（Source-Strup）１６がＵＳ接続されている。
【００２２】
前記半導体チップ２０において、１はＮ＋型シリコン基板、２はＮ＋型シリコン基板の一方の主面に形成されたＮ型のエピタキシャル層、３はエピタキシャル層２の表面に形成されたＰベース領域、４はＰベース領域３の表面に選択的に形成されたＮ＋ソース領域である。５はＰベース領域３の表面からＮ＋ソース領域４の一部を貫いてエピタキシャル層２に達するように形成されたゲートトレンチ、６はＮ＋ソース領域４の表面およびゲートトレンチ５の内面に形成された絶縁ゲート酸化膜（シリコン酸化膜）である。
【００２３】
７ａはシリコン酸化膜６上にＮ型不純物が高濃度にドープされたポリシリコン膜が堆積されてパターニングされたゲートポリシリコン配線、７ｂは上記ポリシリコン膜がゲートトレンチ５内に埋め込まれ、上記ゲートポリシリコン配線７ａに連なるトレンチゲートである。
【００２４】
８はゲートポリシリコン配線７ａの上面の一部を露出させた状態で残り表面を覆う絶縁膜、９はゲートポリシリコン配線７ａの上面の露出部分に形成された例えばＴｉ/ ＴｉＮシリサイド層である。
【００２５】
１０は基板上面を覆う層間絶縁膜、１１は層間絶縁膜１０およびその下層のシリコン酸化膜６およびＮ＋ソース領域４に対してＰベース領域３に達するように選択的に開口されたコンタクト孔、１２はコンタクト孔１１の底部周辺に形成され、Ｎ＋ソース領域４とのオーミックコンタクトをとるための拡散層である。また、チップ周辺部でゲートポリシリコン配線７ａ上のシリサイド層９上の層間絶縁膜１０にコンタクト孔（図示せず）が形成されている。
【００２６】
１３、１４、１４ａは層間絶縁膜１０上にスパッタ蒸着されてパターニングされたメタル（例えばＡｌ）であり、１３は前記コンタクト孔１１を介してＮ＋ソース領域４に連なる表面ソース電極、１４ａは前記チップ周辺部のコンタクト孔（図示せず）を介してゲートポリシリコン配線７ａの上面のシリサイド層９にコンタクトしている配線、１４は上記配線ａに連なる表面ゲート電極（パッド部）となる。なお、Ｎ＋型シリコン基板１の他方の主面（裏面）には、メタル（例えばＡｌ）からなるドレイン（Drain ）電極（図示せず）が形成される。
【００２７】
以下、図１および図２に示した半導体チップ２０のＭＯＳＦＥＴ素子の製造方法の一例について説明する。
【００２８】
まず、Ｎ＋型のシリコンからなる半導体ウェーハ１の主面に、Ｎ型のエピタキシャル層２をエピタキシャル成長により形成する。そして、イオン注入法を用いて前記エピタキシャル層２の表面にＰ型の不純物、例えばボロンを打ち込み、拡散させてＰベース領域３を形成する。
【００２９】
次に、イオン注入法を用いてＮ型の不純物、例えばひ素をＰベース領域３に選択的に打ち込み、拡散させて表面にソース領域４を形成する。
【００３０】
次に、Ｐベース領域３の表面から前記Ｎ＋層４の一部を貫いて前記エピタキシャル層２に達するようにゲートトレンチ５を例えば反応性イオンエッチング（Reactive Ion Etching; ＲＩＥ）法により選択的にエッチングする。
【００３１】
次に、ウェーハ上面を酸化させて絶縁ゲート酸化膜（シリコン酸化膜）６を形成する。
【００３２】
その後、ゲート電極用のＮ型不純物が高濃度にドープされたポリシリコン膜をゲートトレンチ５が十分に埋まるまで堆積し、ゲートの配線部分以外をシリコン表面まで選択的にエッチングする。これにより、ゲートポリシリコン配線７ａおよびトレンチゲート７ｂが形成される。
【００３３】
次に、ウェーハ上面に絶縁膜８をＣＶＤ法により堆積し、パターニングによりゲートポリシリコン配線７ａの一部分を露出させ、その上から例えばＴｉ/ ＴｉＮをスパッタ法により堆積させ、例えば急速熱処理（ＲＴＡ）を加えてシリサイド層９を形成する。
【００３４】
その後、絶縁層間膜１０をＣＶＤ法により堆積し、ソース領域４とのコンタクト孔１１をＲＩＥ法により設け、コンタクト孔１１中にＰ型の不純物、例えばボロンを打ち込み拡散させてソース領域４とのオーミックをとるための拡散層１２を形成する。
【００３５】
その後、表面ソース電極１３、表面ゲート電極１４、配線１４ａとなるメタルをスパッタ法により蒸着する。最後に、ウェーハ裏面にドレイン電極を形成し前記したようなトレンチゲート型パワーＮＭＯＳＦＥＴを得る。
【００３６】
上記実施例のトレンチゲート型のパワーＮＭＯＳＦＥＴは、表面ソース電極１３上にストラップ１６を超音波接続することにより、ストラップ構造の信頼性を向上させることができる。
【００３７】
また、ゲートポリシリコン配線７ａの上面の一部をシリサイド化してシリサイド層９を形成し、このシリサイド層９にコンタクトする配線１４ａを介して表面ゲート電極１４を接続することにより、ゲートＡｌ配線（図４中の４２）を設けた場合と同等の低い値（１．５Ω程度）の素子内部抵抗ｒｇを実現することができる。これにより、従来例で用いていたゲートＡｌ配線（図４中の４２）を省略することができる。
【００３８】
したがって、ストラップ構造でありながらオン抵抗を下げたトレンチゲート型のパワーＮＭＯＳＦＥＴを実現することができる。
【００３９】
＜第２の実施形態＞
図３は、本発明の第２の実施形態に係るストラップ構造を採用したトレンチゲート型のパワーＮＭＯＳＦＥＴの一部を概略的に示す断面図である。
【００４０】
第２の実施形態のパワーＮＭＯＳＦＥＴは、前述した第１の実施形態のパワーＮＭＯＳＦＥＴと比べて、平面パターンは同じであるが、ゲートポリシリコン配線部の断面構造および形成工程が以下に述べるように異なり、その他は同じであるので、図３において図２中と同一部分には同一符号を付している。
【００４１】
即ち、ゲート電極用のＮ型不純物が高濃度にドープされたポリシリコン膜をゲートトレンチ５が十分に埋まるまで堆積し、ゲートの配線部分以外をシリコン表面まで選択的にエッチングしてゲートポリシリコン配線７ａおよびトレンチゲート７ｂを形成するまでは、第１の実施形態と同様である。この後、ウェーハ上面に絶縁膜８を堆積することなく、例えばＴｉ/ ＴｉＮをスパッタ法により堆積させ、ＲＴＡによる熱処理を加えてシリサイド化し、シリサイド層９を形成する。これと同時に、トレンチゲート７ｂのポリシリコン上層部もシリサイド化し、シリサイド層９を形成する。この後、層間絶縁膜１０を形成する。
【００４２】
上記第２の実施形態によれば、ゲートポリシリコン配線７ａの上面の一部を露出させた状態で残り表面を覆う絶縁膜８が省略されており、ゲートポリシリコン配線７ａの上面全面におよびトレンチゲート７ｂのポリシリコン上面にＴｉ/ ＴｉＮシリサイド層９が形成されている。
【００４３】
このような構造でも、前述した第１の実施形態のパワーＮＭＯＳＦＥＴと同等の効果を有する。
【００４４】
なお、上記各実施例では、トレンチゲート型パワーＮＭＯＳＦＥＴを例にとったが、本発明は、トレンチゲート型パワーＰＭＯＳＦＥＴやＩＧＢＴにも上記各実施例に準じて適用可能であることはいうまでもない。
【００４５】
【発明の効果】
上述したように本発明の半導体装置によれば、半導体素子の表面ソース電極上にストラップを超音波接続することでストラップ構造の信頼性を向上させることができるともに、しかも、半導体素子のゲートポリシリコン配線の上面の少なくとも一部をシリサイド化させることでゲートの素子内部抵抗ｒｇを低く維持することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係るストラップ構造を採用したトレンチゲート型のパワーＮＭＯＳＦＥＴの一部を概略的に示す平面図。
【図２】図１中のＢ−Ｂ線に沿う構造を概略的に示す断面図。
【図３】本発明の第２の実施形態に係るストラップ構造を採用したトレンチゲート型のパワーＮＭＯＳＦＥＴの一部を概略的に示す断面図。
【図４】従来のワイヤボンディング構造を採用したトレンチゲート型のパワーＭＯＳＦＥＴの一部を概略的に示す平面図。
【図５】図４中のＢ−Ｂ線に沿う構造を概略的に示す断面図。
【図６】従来提案されているストラップ構造を採用したパワーＭＯＳＦＥＴの一部を概略的に示す平面図。
【図７】図６中のＢ−Ｂ線に沿う構造を概略的に示す断面図。
【符号の説明】
１…Ｎ+ 型半導体基板、
２…Ｎ型エピタキシャル層、
３…Ｐベース領域、
４…Ｎ＋型ソース拡散層、
５…ゲートトレンチ、
６…ゲート酸化膜、
７ａ…ゲートポリシリコン配線、
７ｂ…トレンチゲート、
８…絶縁膜、
９…シリサイド層、
１０…絶縁層間膜、
１１…コンタクト孔、
１２…Ｐ＋型不純物拡散層、
１３…表面ソース電極、
１４…表面ゲート電極、
１５…ゲートワイヤ、
１６…ソースストラップ、
２０…半導体チップ。

Claims (7)

  1. 互いに対向する第１および第２の表面を有し、各々が共通するドレイン領域と、各々がソース領域およびゲート領域を有する複数個のセルを含む半導体チップと、
    前記各ゲート領域を互いに接続し、少なくとも表面の一部にシリサイド層を有するゲートポリシリコン配線層と、
    前記各ソース領域に接続され、絶縁膜を介して前記ゲートポリシリコン配線層を覆うように前記第１の表面に設けられた表面ソース電極と、
    超音波により前記表面ソース電極に結合されたストラップ部材と、
    前記ゲートポリシリコン配線層に接続され、前記第１の表面に設けられた表面ゲート電極と、
    前記第２の表面に設けられ、前記複数個のセルに共通するドレイン電極と
    を具備することを特徴とする半導体装置。
  2. 前記絶縁膜は層間絶縁膜であることを特徴とする請求項１記載の半導体装置。
  3. 前記ゲートポリシリコン配線層に連なるポリシリコンが埋め込まれたトレンチゲートを有し、前記トレンチゲート内のポリシリコンの上部にシリサイド層を有することを特徴とする請求項１又は２記載の半導体装置。
  4. 前記半導体チップはリードフレームに搭載されることを特徴とする請求項１記載の半導体装置。
  5. 前記表面ソース電極はアルミニウム（Ａｌ）を主成分とすることを特徴とする請求項１記載の半導体装置。
  6. 前記ストラップ部材は銅（Ｃｕ）またはアルミニウム（Ａｌ）を主成分とすることを特徴とする請求項１記載の半導体装置。
  7. 前記複数個のセルはＭＯＳＦＥＴおよびＩＧＢＴから選択された１つであることを特徴とする請求項１記載の半導体装置。
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (ja) 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
US6818939B1 (en) * 2003-07-18 2004-11-16 Semiconductor Components Industries, L.L.C. Vertical compound semiconductor field effect transistor structure
JP3906213B2 (ja) * 2004-03-10 2007-04-18 株式会社東芝 半導体装置
JP2006032873A (ja) * 2004-07-22 2006-02-02 Toshiba Corp ストラップボンディング装置及びストラップボンディング方法
US20060163650A1 (en) * 2005-01-27 2006-07-27 Ling Ma Power semiconductor device with endless gate trenches
US20080042208A1 (en) * 2006-08-16 2008-02-21 Force Mos Technology Co., Ltd. Trench mosfet with esd trench capacitor
US20080042222A1 (en) * 2006-08-16 2008-02-21 Force Mos Technology Co., Ltd. Trench mosfet with copper metal connections
US7629646B2 (en) * 2006-08-16 2009-12-08 Force Mos Technology Co., Ltd. Trench MOSFET with terraced gate and manufacturing method thereof
JP2008078561A (ja) * 2006-09-25 2008-04-03 Toshiba Corp 半導体装置及びその製造方法
US8237268B2 (en) * 2007-03-20 2012-08-07 Infineon Technologies Ag Module comprising a semiconductor chip
JP2009081198A (ja) * 2007-09-25 2009-04-16 Toshiba Corp 半導体装置
US20100013009A1 (en) * 2007-12-14 2010-01-21 James Pan Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance
JP2009164183A (ja) 2007-12-28 2009-07-23 Toshiba Corp 半導体装置及びその製造方法
CN101728266B (zh) * 2008-10-15 2011-12-07 尼克森微电子股份有限公司 沟渠式功率半导体的制作方法
DE112010000882B4 (de) * 2009-02-24 2015-03-19 Mitsubishi Electric Corporation Siliziumkarbid-Halbleitervorrichtung
CN101826551B (zh) * 2009-03-03 2012-12-05 M-Mos半导体香港有限公司 具有低栅电阻的沟槽型半导体功率器件及其制备方法
US8143125B2 (en) * 2009-03-27 2012-03-27 Fairchild Semiconductor Corporation Structure and method for forming a salicide on the gate electrode of a trench-gate FET
JP5777319B2 (ja) * 2010-10-27 2015-09-09 三菱電機株式会社 半導体装置
US10438813B2 (en) 2017-11-13 2019-10-08 Alpha And Omega Semiconductor (Cayman) Ltd. Semiconductor device having one or more titanium interlayers and method of making the same
CN109524472A (zh) * 2018-12-29 2019-03-26 华羿微电子股份有限公司 新型功率mosfet器件及其制备方法
US20210343847A1 (en) * 2020-04-30 2021-11-04 Cree, Inc. Diffusion and/or enhancement layers for electrical contact regions

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2944840B2 (ja) * 1993-03-12 1999-09-06 株式会社日立製作所 電力用半導体装置
JP3516789B2 (ja) * 1995-11-15 2004-04-05 三菱電機株式会社 半導体パワーモジュール
JPH10321855A (ja) * 1997-03-18 1998-12-04 Toshiba Corp 高耐圧半導体装置
US6063678A (en) * 1998-05-04 2000-05-16 Xemod, Inc. Fabrication of lateral RF MOS devices with enhanced RF properties
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US6307755B1 (en) * 1999-05-27 2001-10-23 Richard K. Williams Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die
US6545364B2 (en) * 2000-09-04 2003-04-08 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same
JP3639515B2 (ja) 2000-09-04 2005-04-20 三洋電機株式会社 Ｍｏｓｆｅｔの実装構造の製造方法
US6586833B2 (en) * 2000-11-16 2003-07-01 Silicon Semiconductor Corporation Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines

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