TWI470789B - 製備準諧振變換器的單片絕緣閘雙極電晶體及二極體結構及其方法 - Google Patents
製備準諧振變換器的單片絕緣閘雙極電晶體及二極體結構及其方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims description 90
- 239000000758 substrate Substances 0.000 claims description 29
- 230000002093 peripheral effect Effects 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 210000000746 body region Anatomy 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 230000005684 electric field Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 37
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 13
- 229910052721 tungsten Inorganic materials 0.000 description 13
- 239000010937 tungsten Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 7
- 239000007943 implant Substances 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- ZADPBFCGQRWHPN-UHFFFAOYSA-N boronic acid Chemical compound OBO ZADPBFCGQRWHPN-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- WABPQHHGFIMREM-RNFDNDRNSA-N lead-211 Chemical compound [211Pb] WABPQHHGFIMREM-RNFDNDRNSA-N 0.000 description 1
- WABPQHHGFIMREM-BKFZFHPZSA-N lead-212 Chemical compound [212Pb] WABPQHHGFIMREM-BKFZFHPZSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
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Description
本發明主要關於半導體功率元件的結構及製造方法。更確切的說,本發明是關於製備準諧振變換器的新型結構及其方法,藉由將絕緣閘雙極電晶體(IGBT)與橫向二極體相結合,橫向二極體作為單片結構及封裝結構,無需共同封裝單獨的二極體晶片,並且無需特殊的晶圓背部處理。
用於配置及製備準諧振變換器成為功率元件的傳統製程,仍然面臨許多困難與侷限。確切地說,依據行業標準,傳統的諧振變換器通常含有一個絕緣閘雙極電晶體(IGBT)1及一個共同封裝的二極體2,如第1A圖所示。與金屬氧化物半導體場效應電晶體(MOSFET)不同,IGBT元件沒有本征體二極體。在元件底部的P-型集電極層5會阻止將要形成的體二極體傳導,如第1B圖所示。由於需要將兩個單獨的晶片(IGBT及二極體)作為一個共同封裝的部件整合並連接起來,增加了製備成本。此外,IGBT必須做得較小,以便在相同的封裝引腳內能夠容納單獨的二極體晶片。這增加了元件的電阻,降低了電流處理能力。
傳統的準諧振變換器的一種可能的應用就是利用電感加熱的電飯煲。在這種應用中,軟恢復不是二極體必須具備的特性。不需要高性能的二極體;在IGBT接通之前,二極體僅需要傳導一段很短的時間。
如第1C圖所示,已經研發出了反向傳導IGBT,在IGBT晶片的背部附近形成有垂直二極體。P-型集電極層5中的N-型植入區6,形成從IGBT集電極到發射極的P-N結二極體,從元件的底部開始,到頂部與P-型本體區7(或發射極)會合。如第1C圖所示的帶有反平行(反向傳導)垂直二極體的IGBT,需要額外的背部處理,包括在背部形成一個遮罩,用於背部植入。這些額外的背部處理製程,增加了製備成本,而且實施難度更大。在處理薄晶圓時,較薄晶圓的額外的背部處理也增加損壞晶圓的風險。另外,如第1C圖所示,帶有反向傳導垂直二極體結構,使得元件可能在接通時受到突然跳回。
因此,仍然需要研發一種新型的IGBT結構以及封裝結構,以解決本領域的技術人員在功率元件設計及製備領域中遇到的難題及侷限。
本發明的目的是提供一種製備準諧振變換器的新型結構及其方法,藉由將絕緣閘雙極電晶體(IGBT)與橫向二極體相結合,使橫向二極體作為單片結構及封裝結構,無需共同封裝單獨的二極體晶片,並且無需特殊的晶圓背部處理,以解決本領域的技術人員在功率元件設計及製備領域中遇到的難題及侷限。
因此,本發明的一個方面在於,提出了一種新型及改良的元件結構及製備方法,製備與橫向二極體結構相結合的單片IGBT,無需將IGBT晶片與單獨的二極體晶片共同封裝,並且無需為了製備反平行二極體在晶圓上進行背部處理製程。從而改善了準諧振變換器的製備成本以及製備係數。
本發明的另一個方面在於,提出了一種新型及改良的元件結構及製備方法,製備與橫向二極體結構相結合的單片IGBT,利用IGBT元件的通道終止區,形成橫向二極體,從而在IGBT接通時,避免突然跳回問題。
本發明的另一個方面在於,提出了一種新型及改良的元件結構及製備方法,製備與橫向二極體結構相結合的單片IGBT,作為P-i-N二極體,從而可以分別控制P-i-N二極體兩邊的注入效率,獲得很低的反向恢復電荷Qrr,無需傳統的壽命控制過程(例如電子輻照(ER)或金及鉑擴散,形成很深的能級重組位置)。
本發明的另一個方面在於,提出了一種新型及改良的元件結構及製備方法,製備與橫向二極體結構相結合的單片IGBT,利用IGBT元件的通道終止區,形成一個橫向二極體,從而可以配置較大的IGBT晶片,或者由於不需要共同封裝單獨的二極體晶片,因此可以使用較小的封裝尺寸。
本發明的較佳實施例主要提出了一種形成在半導體基板中的垂直半導體功率元件。該垂直半導體功率元件更包括相應的橫向二極體的週邊端,以及設置在半導體功率元件主動區上,與週邊端水準相對的二極體中心端。在進一步的實施例中,半導體元件更包
括一個通道終止區,在半導體基板的週邊附近,其中週邊端在通道終止區接觸半導體基板。在本發明的一個實施例中,半導體功率元件是絕緣閘雙極電晶體(IGBT)。
其中,本發明提出了一種在半導體基板中製備垂直半導體功率元件的方法。該方法包括在半導體元件的截止區中形成週邊端,並形成一個中心端設置在半導體功率元件的主動區中的,以便沿半導體基板的整個水平方向形成一個橫向二極體。為傳播電場(例如浮動保護環)的截止結構,可以設置在主動區及週邊端之間。該方法更包括在引線框的晶片墊上方組裝半導體元件,並將二極體的週邊端藉由帶有導電互聯結構的引線框,連接到半導體元件的底端。
閱讀以下詳細說明並參照圖式之後,本發明的這些及其他的特點及優勢,對於本領域的技術人員而言,無疑將顯而易見。
1、198‧‧‧絕緣閘雙極電晶體
100、100’、100’’‧‧‧垂直絕緣閘雙極電晶體晶片
101‧‧‧集電極端
103‧‧‧P-型集電極層
104、104’‧‧‧輕摻雜層
105‧‧‧N-型緩衝層
110‧‧‧外延層
115‧‧‧閘極絕緣層
120‧‧‧溝槽閘極
120-1‧‧‧閘極墊
125‧‧‧本體區
130‧‧‧源極區
130’‧‧‧N-型區
140、150‧‧‧金屬插頭
141、151‧‧‧接觸溝槽
145‧‧‧P-型區
155、155’‧‧‧P+本體接觸區
160‧‧‧截止結構
165‧‧‧絕緣層
170‧‧‧陽極端
171‧‧‧平面閘極
180‧‧‧陰極端
185‧‧‧導電直通半導體通孔
190‧‧‧主動區
195‧‧‧截止
199‧‧‧反平行二極體
2‧‧‧二極體
200‧‧‧絕緣閘雙極電晶體封裝
201‧‧‧引線框
202‧‧‧晶片墊
211‧‧‧閘極引線
212‧‧‧集電極引線
213‧‧‧陽極引線
215‧‧‧接合引線
5‧‧‧P-型集電極層
6‧‧‧N-型植入區
7‧‧‧P-型本體區
第1A圖係為一種先前技術中與肖特基二極體晶片共同封裝的IGBT晶片的封裝佈局之俯視圖。
第1B圖係為傳統之IGBT之剖面圖。
第1C圖係為傳統之IGBT之剖面圖,具有形成在其背部的反向傳導二極體。
第2A圖係為本發明之單片IGBT及二極體結構之剖面圖,其中將溝槽MOSFET及橫向二極體相結合。
第2B圖係為第2A圖所述之IGBT元件之等效電路圖。
第2C圖係為本發明之一個較佳實施例之剖面圖。
第2D圖係為本發明之另一個較佳實施例之剖面圖。
第3圖係為第2A圖所述IGBT元件之封裝佈局之俯視圖。
第4A至4F圖係為製備第2A圖所述IGBT元件之製程之剖面圖。
第5A至5D圖係為製備類似於第2A圖所述IGBT元件之製程之剖面圖。
第2A圖所示之剖面圖表示本發明所述的與橫向二極體結構整合的垂直絕緣閘雙極電晶體(IGBT),作為IGBT晶片100。作為示例,IGBT可以含有帶有橫向二極體的溝槽金屬氧化物半導體(MOS)閘極。與橫向二極體相結合的溝槽MOS結構,形成在半導體基板中,集電極端101連接到P-型集電極層103下方的背部表面,P-型集電極層103設置在基板底部。基板包括一個N-型層,位於P-型集電極層103上方;作為示例,如第2A圖所示,這個N-型層包括一個N-型緩衝層105,位於P-型集電極層103上方,以及一個輕摻雜的N-型層(例如N-型外延層110),位於N-型緩衝層105上方。N-型緩衝層105比N-型外延層110更加重摻雜。與橫向二極體相結合的IGBT更包括一個溝槽閘極120,墊有閘極絕緣層115,覆蓋在溝槽的側壁及底面上方。溝槽閘極120在P-型本體區125(即發射極區)附近,包圍著N+源極區130,緊鄰外延層110頂面附近的閘極。
IGBT晶片100更包括一個主動區190及一個截止區195。整合的橫向二極體從主動區190開始,水準延伸到截止區195。源極、本體或陽極接觸溝槽也形成在外延層110中,發射極或陽極端170形成在第一導電金屬插頭140(例如鎢)上方,輕摻雜的P-型區145形成在金屬插頭140下方。發射極或陽極端170(藉由鎢金屬插頭
140)接觸源極區130及本體區125。本體區125可以補充輕摻雜的P-型區145以及重摻雜的P+本體接觸區155。輕摻雜的P-型區145構成低注入效率的P-N二極體,帶有外延層110及N-型區130’。二極體可以看成是P-i-N(P-型-本征-N-型)二極體,P-型區145作為二極體的陽極,輕摻雜的N-型外延層110作為二極體的本征部分,N-型區130’作為二極體的陰極。陰極端180形成在第二鎢金屬插頭150上方,輕摻雜P-型區145形成在金屬插頭150下方,金屬插頭150設置在截止區195週邊的半導體基板的周圍附近。截止區195更包括一個較佳的截止結構(例如P-型保護環)160。截止結構160用於將截止電場在觸及晶片邊緣之前,橫向擴展至整個截止區195。二極體陰極端180可以在截止結構160的週邊。P+本體接觸區155、155’更形成在鎢金屬插頭140、150附近,鎢金屬插頭140、150在主動區190中的源極區130下方,N-型區130’在陰極端180下方的鎢金屬插頭150附近。作為示例,N-型區130’可以是一個通道終止區,位於IGBT晶片100的週邊附近。絕緣層165可以在發射極或陽極端170及陰極端180之間延伸,覆蓋著鎢金屬插頭140及鎢金屬插頭150之間的外延層110的頂面。結合的橫向二極體作為受控的反向恢復(即受控的反向恢復電荷(Qrr))二極體,無需傳統的壽命控制方法。第2A圖所示的二極體為低注入效率的P-N結二極體,形成于接觸溝槽下方的輕摻雜的P-型區145,以及N-型外延層110,然後穿過P-型區145,到達陰極端180。此外,重摻雜的P+本體接觸區155的尺寸很小,限制了從本體區注入的載流子的量。即使二極體的P-N結是垂直形成的,二極體陰極端180位於截止區195中,橫向遠離主動區190中的二極體陽極端170,因此可以認為該二極體是一個橫向二極體
。重摻雜的N-型區130’可以與源極區130同時形成,並且可以為陰極鎢金屬插頭150提供良好的接觸。重摻雜的P+本體接觸區155’可以與P+本體接觸區155同時形成,可以有助於控制來自N-型區130’在二極體的陰極端的注入效率。也可以設計N-型區130’的尺寸,減少來自N-型區130’的載流子注入。因此,該橫向二極體與IGBT單片整合,無需第1C圖所示的傳統結構中所需的進一步的背部處理。陰極端180及鎢金屬插頭150可以作為二極體的週邊端,陽極端170及鎢金屬插頭140可以作為橫向二極體的中心端。
該元件包括一個垂直的絕緣閘雙極電晶體(IGBT),其集電極端101設置在底部,發射極或陽極端170設置在鎢金屬插頭140上方的頂面上。
第2B圖所示之電路圖表示第2A圖之IGBT晶片100之等效電路圖。IGBT 198與反平行二極體199連接在一起。第2B圖與第2A圖相比,IGBT 198位於IGBT晶片100的主動區190中,從發射極或陽極端170到集電極端101,形成的反平行二極體199從主動區190中的發射極或陽極端170到截止區195中的陰極端180。陰極端180可以內部或外部連接到集電極端101上。
第2C圖所示之剖面圖表示IGBT晶片100’,除了包括一個導電直通半導體通孔(TSV)185,將二極體的陰極端180電連接到集電極端101之外,其他都與第2A圖所示的IGBT晶片100類似。作為示例,TSV 185可以包括絕緣側壁。
第2D圖表示本發明的一個較佳實施例之剖面圖。IGBT晶片100’
’除了具有平面閘極171,而不是溝槽閘極120之外,其他都與第2A圖所示的IGBT晶片100類似。整合的橫向二極體從發射極或陽極端170,到N-型外延層110內的P-型本體區125,並橫向穿入截止區195(例如在N-型區130’中)的陰極端180內。
第3圖所示之俯視圖表示IGBT封裝200的結構,單片IGBT以及引線框201上的IGBT晶片100(與第2A圖中類似),與閘極引線211相結合,連接到IGBT晶片100的閘極墊120-1上,陰極或集電極引線212連接到IGBT的陰極端180以及整合的IGBT晶片100,發射極或陽極引線213連接到IGBT的發射極或陽極端170以及整合的IGBT晶片100。作為示例,這些部分可以藉由接合引線215、夾片或任意其他導電互聯結構連接起來。由於IGBT晶片100直接安裝在引線框201的晶片墊202上方,並且由於陰極或集電極引線連接在晶片墊202上,因此引線框201的陰極或集電極引線212在IGBT以及整合的IGBT晶片100的底面,也直接連接到集電極端101上(第3圖沒有表示出)。因此,IGBT晶片100的集電極端101以及陰極端180在外部連接在一起。
第4A至4F圖所示之剖面圖表示與第2A圖所示相類似的IGBT晶片100的IGBT的製備製程。第4A圖表示P-型集電極層103位於N-型緩衝層105下面,N-型層(例如外延層110)位於N-型緩衝層105上方。在第4B圖中,具有溝槽閘極120閘極電極及閘極絕緣層115閘極電介質的閘極溝槽結構,形成在N-型外延層110的頂部。在第4C圖中,製備P-型本體區125(以及可選浮動保護環的截止結構160)以及N-型源極區130及N-型區130’。作為示例,源極區130及N-型區130’可以在同一個植入製程中製備,P-型本體區125以
及P-型浮動環的截止結構160可以在同一個植入製程中製備。絕緣層165(例如含有硼酸的矽玻璃(BPSG))形成在晶片的頂部上方。形成BPSG絕緣層165的圖案,接觸溝槽141、151部分形成在N-型外延層110內,刻蝕到源極區130及本體區125中。重摻雜的P+本體接觸區155、155’形成(例如植入及擴散)在部分刻蝕的接觸溝槽141、151底部,如第4D圖所示。然後,進一步向下刻蝕部分刻蝕的接觸溝槽141、151,以便穿過絕大部分的P+本體接觸區155垂直刻蝕,觸及輕摻雜的N-型外延層110。在接觸溝槽的邊緣處,僅保留一小部分的重摻雜P+本體接觸區155。在這種情況下,輕摻雜的P-型區145可以形成(例如植入)在接觸溝槽141、151的底部,以製備元件的低注入效率的P-N二極體,如第4E圖所示。導電金屬插頭(例如鎢)140、150填充接觸溝槽,製備一個金屬層並形成圖案,以製備發射極或陽極端170以及陰極端180。集電極端101形成在元件的背面,P-型集電極層103,如第4F圖所示。
第5A至5D圖所示之剖面圖表示製備IGBT晶片100的較佳製程,從一種不同的半導體基板裝置開始。在第5A圖中,初始的半導體基板相對較厚,輕摻雜層104位於N-型緩衝層105下方,輕摻雜N-型層(例如外延層110)位於N-型緩衝層105上方。進行上述第4B至4F圖所述的正面處理製程,完成元件的正面,如第5B圖所示;但是,集電極端101還沒有在背面形成。反而背部研磨相對較厚的輕摻雜層104,以形成一個很薄的輕摻雜層104’,如第5C圖所示。然後,大量的P-型植入在元件底部形成P-型集電極層103,隨後形成集電極端101,如第5D圖所示。還可選擇,進行背部研磨
以及接下來的集電極植入,使製程的最後不保留很薄的輕摻雜層104’(即沒有輕摻雜區104’在中間,P-型集電極層103直接接觸N-型緩衝層105)。
儘管本發明已經詳細說明了現有的較佳實施例,但應理解這些說明不應作為本發明的侷限。本領域的技術人員閱讀上述詳細說明後,各種變化及修正無疑將顯而易見。例如,儘管上述內容說明的是n-通道IGBT元件,但是藉由轉換半導體區域的導電類型(例如從N-型轉換成P-型,反之亦然),本發明也可應用於P-通道元件。因此,應認為申請專利範圍涵蓋本發明的真實意圖及範圍內的全部變化及修正。
100‧‧‧垂直絕緣閘雙極電晶體晶片
101‧‧‧集電極端
103‧‧‧P-型集電極層
105‧‧‧N-型緩衝層
110‧‧‧外延層
115‧‧‧閘極絕緣層
120‧‧‧溝槽閘極
125‧‧‧本體區
130‧‧‧源極區
130’‧‧‧N-型區
140、150‧‧‧金屬插頭
145‧‧‧P-型區
155、155’‧‧‧P+本體接觸區
160‧‧‧截止結構
165‧‧‧絕緣層
170‧‧‧陽極端
180‧‧‧陰極端
190‧‧‧主動區
195‧‧‧截止區
Claims (16)
- 一種半導體元件結構,其包含:一形成在一半導體基板中之一垂直半導體元件;一位於該垂直半導體元件之一截止區中之一二極體之一週邊端;一設置在該垂直半導體元件之一主動區中之該二極體之一中心端,其橫向遠離該二極體之該週邊端;其中,該二極體之該週邊端更包含一導電插頭,其填充在該半導體基板週邊附近之一週邊溝槽中,並且被設置在該導電插頭上方之陰極一金屬接頭覆蓋,其中該週邊溝槽接觸一第一導電類型之一上部摻雜區及在該上部摻雜區下面之一第二導電類型之一次重摻雜區。
- 如申請專利範圍第1項所述之半導體元件結構,其中該第一導電類型之該上部摻雜區形成該垂直半導體元件的一通道終止區,位於該半導體基板週邊附近之該垂直半導體元件之該截止區中,該二極體的該週邊端在該通道終止區接觸該半導體基板。
- 如申請專利範圍第1項所述之半導體元件結構,其中該垂直半導體元件是一與該二極體整合之垂直絕緣閘雙極電晶體,該二極體設置在水平方向上,從該垂直絕緣閘雙極電晶體之該主動區到該截止區。
- 如申請專利範圍第1項所述之半導體元件結構,更包含:一電場傳播截止結構,設置在該垂直半導體元件之該主動區及該二極體之該週邊端之間之該垂直半導體元件之該截止區中。
- 如申請專利範圍第1項所述之半導體元件結構,其中該二極體之該中心端更包含一第二導電插頭,其填充在該半導體基板之該主動區中之中心一接觸溝槽中,被設置在該第二導電插頭上方之中心一金屬接頭覆蓋。
- 如申請專利範圍第1項所述之半導體元件結構,其中該垂直半導體元件是一與該二極體相結合之垂直絕緣閘雙極電晶體,該二極體在水平方向上設置,從該垂直絕緣閘雙極電晶體之該主動區橫跨到該截止區中之該週邊端,其中該垂直絕緣閘雙極電晶體包含一設置在該半導體基板底面上之集電極端,以及一設置在該半導體基板頂面上之發射極端,其中該發射極端是該二極體之該中心端。
- 如申請專利範圍第6項所述之半導體元件結構,其中該垂直絕緣閘雙極電晶體形成在該第一導電類型之一第一半導體層中,且該垂直絕緣閘雙極電晶體更包含一在該主動區中之閘極,該閘極在該第二導電類型之一本體區附近,該本體區包圍著該第一導電類型之一源極區,其中該垂直絕緣閘雙極電晶體更包含一第二導電類型之一集電極層,位於該第一半導體層下方。
- 如申請專利範圍第7項所述之半導體元件結構,更包含:該第一導電類型之一緩衝層,位於該集電極層及該第一半導體層之間,其中該緩衝層比該第一半導體層摻雜濃度更高。
- 如申請專利範圍第6項所述之半導體元件結構,更包含:一設置在該第一半導體層中之截止結構,位於該垂直絕緣閘雙極電晶體之該主動區及該二極體之該週邊端之間。
- 一種半導體元件結構,其包含:一形成在一半導體基板中之垂直半導體元件; 一位於該垂直半導體元件之一截止區中之一二極體之週邊端;一設置在該垂直半導體元件之一主動區中之該二極體之中心端,其橫向遠離該二極體之該週邊端;其中,該垂直半導體元件是一與該二極體相結合之垂直絕緣閘雙極電晶體,該垂直絕緣閘雙極電晶體形成在一第一導電類型之一第一半導體層中,且該垂直絕緣閘雙極電晶體更包含一在該主動區中之閘極,該閘極在一第二導電類型之一本體區附近,該本體區包圍著該第一導電類型之一源極區,其中該垂直絕緣閘雙極電晶體更包含該第二導電類型之一集電極層,位於該第一半導體層下方;該二極體之該中心端更包含一導電插頭,其填充在一中心溝槽中,接觸該垂直絕緣閘雙極電晶體之一本體區及一源極區,並且被設置在該導電插頭上方之發射極或陽極一金屬接頭覆蓋;以及該第二導電類型之一輕摻雜區設置在該第一半導體層中,緊靠著該中心溝槽之底面下方,使該二極體成為低注入效率之二極體。
- 如申請專利範圍第10項所述之半導體元件結構,更包含:一穿過該半導體基板打開之導電通孔,作為一直通半導體通孔,將該二極體之該週邊端內部連接到該集電極端。
- 如申請專利範圍第10項所述之半導體元件結構,更包含:一通道終止區,位於該半導體基板週邊附近之該半導體元件之該截止區中,其中該二極體之該週邊端在該通道終止區接觸該半導體基板。
- 一種用於垂直半導體元件之封裝結構,其中:該垂直半導體元件形成在一半導體基板中,在該垂直半導體元件之一截止區中具有一橫向二極體之一週邊端,在該週邊端之橫向 對面具有該橫向二極體之一中心端,該中心端設置在該垂直半導體元件之一主動區上;以及一引線框藉由一導電互聯結構連接到該橫向二極體之該週邊端及該中心端及該垂直半導體元件上。
- 如申請專利範圍第13項所述之封裝結構,其中該垂直半導體元件是一垂直絕緣閘雙極電晶體,其與從該垂直絕緣閘雙極電晶體之該主動區到該截止區橫向設置之該橫向二極體相結合,其中該垂直絕緣閘雙極電晶體包含一設置在該半導體基板底面上之集電極端,以及一設置在該半導體基板頂面上之發射極端;以及該引線框包含一晶片墊,用於支撐該半導體基板之底面,並且接觸該垂直絕緣閘雙極電晶體之該集電極端。
- 如申請專利範圍第14項所述之封裝結構,更包含:該導電互聯結構,藉由該晶片墊,將該橫向二極體之該週邊端電性連接到該垂直絕緣閘雙極電晶體元件之該集電極端。
- 一種用於製備半導體元件結構之方法,其包含:在一半導體基板中製備一垂直半導體元件,其中將一橫向二極體及該垂直半導體元件整合;在該垂直半導體元件之一截止區中形成該橫向二極體之一週邊端;以及在該垂直半導體元件之一主動區中形成該橫向二極體之一中心端,與該橫向二極體之該週邊端橫向分開;其中,製備該半導體元件之步驟是指製備一垂直絕緣閘雙極電晶體,其中該橫向二極體從該垂直絕緣閘雙極電晶體之該主動區橫向設置到該垂直絕緣閘雙極電晶體之該截止區,該垂直絕緣閘雙極電晶體之一集電極端形成在該半導體基板之底面上,一發射極 端形成在該半導體基板之頂面上;所述之方法,更包含:在一引線框之一晶片墊上組裝該垂直絕緣閘雙極電晶體,該晶片墊電性連接該垂直絕緣閘雙極電晶體之該集電極端;以及將一導電互聯結構從該橫向二極體之該週邊端連接到該引線框,從而藉由該晶片墊,將該橫向二極體之該週邊端電性連接到該垂直絕緣閘雙極電晶體之該集電極端。
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