CN110520999B - 芯片级封装的具有金属填充的深沉降区触点的功率mosfet - Google Patents

芯片级封装的具有金属填充的深沉降区触点的功率mosfet Download PDF

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CN110520999B
CN110520999B CN201680086101.2A CN201680086101A CN110520999B CN 110520999 B CN110520999 B CN 110520999B CN 201680086101 A CN201680086101 A CN 201680086101A CN 110520999 B CN110520999 B CN 110520999B
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layer
metal
semiconductor device
sinker
contact
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CN110520999A (zh
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刘运龙
杨红
H·林
吕天平
邹胜
Q·贾
熊育飞
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Texas Instruments Inc
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Abstract

一种形成包含功率半导体装置的IC(180)的方法包含：提供衬底(100)，所述衬底在其上具有外延层(150)，所述外延层具有形成于其中的被金属前电介质PMD层(118)覆盖的至少一个晶体管(160)。从接触开口蚀刻穿过所述PMD到所述外延层中以形成延伸到所述装置的第一节点的沉降区沟槽。沉积金属填充材料(128b)以覆盖所述沉降区沟槽的侧壁和底部，但不完全填充所述沉降区沟槽。在所述金属填充材料上方沉积电介质填料层(128c)以填充所述沉降区沟槽。移除所述电介质填料层的覆盖层区域，在所述覆盖层区域中的所述金属填充材料的表面上停止以形成沉降区触点(128)。形成图案化互连金属，从而在所述互连金属与所述沉降区沟槽的所述侧壁上的金属填充材料之间提供连接。

Description

芯片级封装的具有金属填充的深沉降区触点的功率MOSFET
技术领域
所揭示的实施例涉及垂直功率半导体装置。
背景技术
在功率集成电路(IC)中，大功率晶体管经常占据芯片面积的主要部分。垂直大功率装置比水平大功率装置占据的面积小，但需要触点将电流从掩埋式漏极或掩埋式集电极运送到衬底表面。通常，通过在一系列不同的能量处植入掺杂剂形成沉降区触点，以形成从衬底的顶表面向下延伸到掩埋式漏极或掩埋式集电极的高掺杂扩散柱。即使在操作期间有沉降区触点扩散，但当大电流流经扩散柱时，可能出现明显的电压降，这可以限制垂直大功率晶体管的性能。
为了提高性能，IC上的一些装置要求低接触电阻。通常为了减小接触电阻，增大扩散面积并且形成多个触点以进行扩散。这增加IC的面积并且还可以增加扩散电容，这可能降低IC的性能。
发明内容
提供本发明内容以便以简化形式介绍在下文中在包含所提供的附图的具体实施方式中进一步描述的所揭示概念的简要集合。本发明内容不旨在限制所主张的主题的范围。
在功率场效应晶体管(FET)芯片级封装(CSP)装置中，公认的是，通常需要从装置的顶表面向下延伸到掩埋式漏极(对于金属氧化物半导体场效应晶体管(MOSFET))或掩埋式集电极(对于双极型装置)的深的低电阻沉降区触点以提供到装置的顶表面的低电阻连接。这使所有装置端子能够以焊料凸块(例如，键合焊盘上的凸块)的形式处于管芯的顶表面上。对于中压功率FET装置来说，公认的是，已知的沉降区触点工艺由于由小临界尺寸(CD)和沉降区触点的深度为至少数μm产生的高电阻而不再足以产生中压产品设计所需的低接通(ON)电阻。由于用于支撑中压产品的较厚外延层(epi)而可能需要很深的沉降区触点(>5μm)(例如，对于40V额定装置，epi的厚度可以为约5.8μm，并且对于60V额定装置，epi更厚，如厚度为约7.2μm)。
所揭示的实施例包含形成沉降区触点的方法，所述方法使用金属填充材料加工仅部分地填充沉降区沟槽，然后是内部电介质填料层(例如，旋涂玻璃(SOG)和/或其它电介质材料)沉积工艺以完成对沉降区沟槽的填充。金属填充材料提供低电阻触点，因为电接触是沿着沉降区触点的整个侧壁区域和底部进行的，而内部电介质填料独立于沉降区深度和沉降区面积而执行基本上完全填充沉降区触点的功能。
当使用已知的深沉降区触点工艺时，特别是当触点大小很大且深度显著增加时，这种加工实现显著较宽且较深的沉降区触点，所述沉降区触点克服触点金属(例如，W)填充——包含半导体(例如，Si)侧壁屏障层覆盖和金属缝(空隙区域)的已知挑战。所揭示的方法还可以将沉降区触点的深度扩展到更广的范围，并且仍然可以提供低电阻以满足各种不同的产品设计需求。更一般地，所揭示的方法可以提供覆盖宽范围的深度的沉降区触点以满足不同的FET或双极设计要求。
附图说明
现在将参考附图，附图不一定按比例绘制，在附图中：
图1是根据实例实施例的集成电路(IC)的横截面图，所述集成电路具有包含所揭示的沉降区触点的实例功率N沟道金属氧化物半导体(NMOS)晶体管。
图2是包含所揭示的沉降区触点的实例功率NMOS晶体管的横截面图。
图3是包含所揭示的沉降区触点的实例功率NMOS晶体管的横截面图。
图4A到图4H是图3中示出的连续制造阶段中描绘的功率NMOS晶体管的横截面图，其中图4D到4H描绘了仅形成第一和第二深沉降区的所揭示的深沉降区加工。
图5是具有到其漏极的所揭示的沉降区触点的功率NMOS晶体管的横截面图。
图6是具有到其集电极的所揭示的沉降区触点的功率NPN双极晶体管的横截面图。
具体实施方式
参照附图描述实例实施例，其中相同参考标号用于表示相似的或等效元件。动作或事件的图示顺序不应被认为是限制性的，因为一些动作或事件可能以不同的顺序和/或与其它动作或事件同时发生。进一步地，一些图示的动作或事件可能不需要实施根据本公开的方法。
而且，如在没有进一步限制的情况下本文所使用的术语“耦合到”或“与……耦合”(等等)旨在描述间接或直接的电气连接。因此，如果第一装置“耦合”到第二装置，则这种连接可以通过路径中只有寄生现象的直接电气连接，或者通过经由包含其它装置和连接的介入项的间接电气连接。对于间接耦合，介入项通常不修改信号的信息，但可以调节其电流电平、电压电平和/或功率电平。
图1是包含实例功率半导体装置的IC 180的横截面图，所述实例功率半导体装置包括垂直功率NMOS晶体管160，所述晶体管具有两个所揭示的低电阻沉降区触点(沉降区触点)128，示出为其掩埋式漏极。虽然本文总体上描述了NMOS和NPN晶体管，但是对于所属领域的普通技术人员明显的是，使用此信息通过p-掺杂取代n-掺杂区域，也形成PMOS晶体管和PNP晶体管，并且反之亦然。所述功率半导体装置可以因此包括以沟槽栅或平面栅布局的PMOS或NMOS装置，或者PNP或NPN垂直双极型装置，或者更一般地任何装置(无论分立的或在IC上)，所述装置需要从掩埋式装置端子(例如，其上具有epi层的衬底中的掩埋式端子)连接到管芯的顶表面上作为电气节点。具有典型的掺杂级为5x 1015cm-3到1x 1017cm-3的n-型外延(epi)层150在具有典型的掺杂级为约1x 1018cm-3到5x 1019cm-3的低电阻重n+掺杂层上，其中n+掺杂层被示出由可能约500μm厚的大型n+衬底100提供。衬底100和epi层150均可以包括硅、硅锗或另一种半导体材料。
沉降区触点128延伸穿过epi层150(例如，作为实例大约5μm厚)并进入所述衬底100。沉降区触点128通常由屏障金属内衬128a加衬。屏障金属内衬128a包括难熔金属层或难熔金属层堆叠，如在一个特定实施例中600A的钛上800A的锡。屏障金属内衬128a还存在于沉降区触点的底部。
沉降区触点128用金属填充材料128b连同内部电介质填料层128c进一步填充，所述金属填充材料如化学气相沉积(CVD)的钨(W)或电镀铜(在铜种子上)，所述内部电介质填料层如金属填充材料128b上的氧化硅。金属填充材料128b的典型厚度范围是0.1μm到1μm。电介质填料层128c的厚度基于沉降区沟槽的尺寸，因为电介质填料层128c完成沉降区沟槽的填充。除了W和铜，金属填充材料128b还可以包括如Ta等其它金属、或如Pt或Pd等铂族金属(PGM)、其金属硅化物、或包含Ti-W的这种金属的金属合金。沉降区触点128沿沉降区触点的侧壁和底部形成电气触点，所述沉降区触点如示出的延伸穿过epi层150进入衬底100。沉降区触点128可以是圆形或矩形形状。
epi层150中衬底100上方示出的2条水平虚线被提供用于指示掺杂剂(例如，用于n+衬底的磷或砷)从衬底100向上扩散到epi层150。虽然沉降区触点128被示出为到达衬底100，但是如果沉降区触点128到达接近(即在0.5μm到1μm内)epi层150/衬底100界面，则这可能足以提供低电阻，因为epi层150的在沉降区触点128下面的部分可能是足够重掺杂的。
为了说明所揭示的沉降区触点128的一些好处，作为实例使用功率NMOS晶体管160。如上所述，还可以使用如功率PMOS晶体管或分立垂直功率双极晶体管等其它晶体管。此外，如上所述，晶体管可以是分立装置或如示出的是IC的一部分。功率NMOS晶体管160的源极是n-型扩散区112。NMOS晶体管160的主体是p-阱，其为NMOS晶体管160提供主体区域(主体)104。功率NMOS晶体管160的漏极是epi层150加衬底100。栅极电介质108使晶体管栅电极110与n-型扩散区112、漏极的epi层150以及NMOS晶体管160的主体104电隔离。示出了电介质隔离层106，如LOCOS(硅的局部氧化)层或STI(浅沟槽隔离)层，所述介质隔离层使功率NMOS晶体管160与沉降区触点128电隔离。
主体104通过接触插塞126连接到互连引线140。由屏障金属层134(例如，TiN或TaN)框住的接触插塞126通过重掺杂p-型扩散区114连接到p-型主体104。n-型扩散区112通过源极接触插塞124连接到互连引线138，所述互连引线与互连引线140和142以及所有其它引线一样作为实例可以包括铝或铜。到主体104的接触孔124'被蚀刻穿过金属前电介质(PMD)层118，所述预金属介电层通常用如钛加氮化钛(Ti/TiN)等屏障金属层134填充，并且然后用如CVD-W等金属材料填充。
在操作期间，当相对于所述主体104施加足够的电压到功率NMOS晶体管160的栅电极110时，对于增强装置，在所述主体104内邻近栅极介电层108处形成通道，并且大电流从作为源极的n-型扩散区112流过功率NMOS晶体管160的通道，并且进入漏极的衬底100区域。由于I＝V/R(电流＝电压/电阻)，因此当常规沉降区触点的接触电阻较大时，由功率NMOS晶体管160提供的电流减小。
沉降区触点128被示出为从第一互连层142垂直延伸穿过PMD层118，穿过epi层150进入如上所述高掺杂的衬底100。这显著降低了与功率NMOS晶体管160串联的接触电阻。降低的电阻导致在此作为NMOS晶体管160的功率装置的大功率(大电流)性能显著提高。
图1中示出的功率NMOS晶体管160的简化版本在图2中被示出为功率NMOS晶体管160'。图1和图2中的对应结构用相同的数字标注。源极/主体触点124、124'是通过蚀刻源极触点穿过作为源极112的n-型扩散区112并且进入p-型主体104而形成的。在这个版本中，作为源极的n-型扩散区112被短路到垂直NMOS晶体管160的主体104，所述晶体管使所述主体二极管失效，并且使MOS晶体管的面积减小。任选的作为p-型扩散区114的p+扩散区可以在源极/主体触点124、124'下形成。功率NMOS晶体管160'是单向的，其中沉降区触点128是其漏极端子。
图1中功率NMOS晶体管的另一简化版本在图3中示出为功率NMOS晶体管160”。在这个版本中，p-阱触点126与源极触点124分离。源极触点124仅作为源极蚀刻到n-型扩散区112，并且不像图2中那样进入主体104。功率NMOS晶体管160”是双向的。沉降区触点128可以用作低电阻漏极触点或低电阻源极触点。当Vcc连接到所述n-型扩散区112并且Vdd连接到沉降区触点128时，则n-型扩散区112是源极并且沉降区触点是垂直NMOS晶体管160”的漏极。当Vcc连接到沉降区触点128并且Vdd连接到n-型扩散区112时，则沉降区连接到源极并且n-型扩散区112是功率NMOS晶体管160”的漏极。
图3中示出的具有沉降区触点128的功率NMOS晶体管160”的主要制造步骤如以下图4A到4C所描述的，在深沉降区工艺中，在图4D到4H中仅示出形成第一和第二深沉降区。提供了衬底100，所述衬底在其上具有epi层150，所述epi层具有被形成为包含在epi层150内的并且被PMD层118覆盖的至少一个晶体管。使用掩蔽层120(例如，光致抗蚀剂)在PMD 118上形成包含图案开口122的第一接触图案，形成所述图案开口对于MOS装置来说用于源极和p阱触点，并且对于双极型装置来说用于发射极和基极触点。例如，然后蚀刻接触开口穿过PMD层118，以到达功率NMOS晶体管的源极，并且到达如图4B中示出的p+p-阱主体触点。
图4B示出了蚀刻后的NMOS晶体管，以形成用于源极接触插塞124的源极接触开口124a，用于主体接触插塞124'的主体接触开口124a'，以及用于如图4C中示出的主体接触插塞126的126a。在图4C中，在装置上还形成了单独的第二沉降区接触图案130，至少形成了一个开口，示出为沉降区沟槽128'，其中待形成沉降区触点128。沉降区沟槽128'被蚀刻穿过PMD层118、穿过epi层150并且通常进入(或几乎到达)衬底100。沉降区沟槽128'以及因此沉降区触点128的深度通常至少是2μm，并且取决于epi层150的厚度，所述厚度可以是5或7μm厚，或更厚。代替具有仅作为接触底部的接触面积，沉降区触点128的接触面积包含沉降区触点128的底部和沉降区触点的整个侧壁区域，所述整个侧壁区域穿过epi层150的完整厚度进入衬底100。如图4C中示出的，沿着沉降区触点128的侧壁和底部示出具有与衬底相同的掺杂类型(在此实例中n-型)的任选的植入区域132以添加掺杂剂从而进一步减小电阻。然后移除第二接触图案130。
虽然未示出，但是在沉积金属填充材料128b之前，上述屏障金属内衬128a通常沉积到接触开口中，以向沉降区沟槽128'加衬。然后沉积金属填充材料(温度：例如，CVD W)128b，其中如图4D中示出的，金属填充材料128b覆盖沉降区沟槽的侧壁和底部，但未完全填充沉降区沟槽。金属填充材料128b通常填充沉降区沟槽底部之上的<50％的接触面积，但是可以提供在任何部分中，如例如从20％到50％的范围内。在PMD 118下方示出了垫氧化物118a。
在金属填充材料128b上沉积电介质填料层128c，其中如图4E中示出的，电介质填料层128c完全填充沉降区沟槽。电介质填料层128c可以包括SOG、原硅酸四乙酯(TEOS)或高密度等离子体(HDP)CVD，用于在沉积金属填充材料128b(例如，CVD W)之后填充其余的接触开口。液态形式的SOG沉积在晶片上时被认为在固化后提供极好的沟槽填充性能，以提供烧结SOG。烧结SOG衍生层具有独特的微结构(例如，相比于CVD氧化物)，因为所述层由于水和溶剂在形成期间通过互连孔蒸发而具有微孔隙度，所述孔在表面处保持部分开启，这是因为完全移除微孔隙度需要加热到在所揭示的SOG加工中通常未被提供的约1000℃。在一个实施例中，电介质填料层128c包含外部CVD内衬介质，如使用TEOS沉积，接着是具有不同于CVD氧化物的微孔隙度的较厚的内部烧结SOG涂层。
移除了电介质填料层128c的覆盖层区域，如通过干燥(例如，等离子体)氧化物回蚀刻或通过停止在所述覆盖层区域中的金属填充材料128b的表面上化学机械抛光(CMP)。图4F中示出了氧化回蚀刻工艺所产生的结构。回蚀刻所述金属填充材料128b，以移除所述覆盖层区域，产生的结构在图4G中示出。图案化互连金属层170被示出为形成以提供互连金属层170与沉降区侧壁上的金属填充材料128b之间的连接，产生的结构在图4H中示出。
使用仅部分填充随后由电解质(例如SOG)填充的沉降区沟槽的金属填充材料128b实现显著更宽且更深的沉降区接触，这克服了使用已知的深沉降区接触工艺尤其是当接触大小和深度显著增加时接触屏障/金属填充(例如，W)覆盖的重大挑战。所揭示的方法还可以降低沉降区触点的纵横比并且将沉降区触点的深度扩展到更广的范围，并且仍然为各种不同的产品设计需求提供低电阻沉降区触点。
具有所揭示的沉降区触点128的平面高功率NMOS晶体管500在图5中被示出为在衬底100上的外延层150上形成。通常，衬底100的背面是漏极。在一些电路中，这呈现了向半导体装置/IC的上部和底部均提供电力以及使在功率NMOS晶体管500操作期间产生的热量散热的问题。
如图5中示出的，沉降区触点128用于将重掺杂衬底100或其它掩埋式n+层电连接到使用仅上部触点的电源。功率NMOS晶体管500的源极508是重掺杂的n-型扩散区，而主体506(例如，p阱)通过重掺杂的p-型扩散区504和触点516短路到源极508。当关于主体506将足够的电压施加到位于栅极介电层108上的栅电极505时，在主体506内在所述栅电极505下形成通道，并且电流流经n-型漏极扩散区510、n-掺杂沉降区扩散区512以及被示出为衬底100的重掺杂n-型层。
沉降区触点128将衬底100和n-掺杂沉降区扩散区512连接到上部互连522。上部互连520被示出耦合到p-型扩散区504。沉降区触点128使Vcc和Vdd均能够从功率NMOS晶体管500的上部供应。具有沉降区触点128的功率NMOS晶体管500被示出为具有源极/主体短路触点的单向NMOS晶体管。虽然图5示出了具有沉降区触点128的功率MOS晶体管500，但是其同样可以很好地用双向NMOS大功率晶体管或单向或双向PMOS大功率晶体管来说明。
图6示出了具有所揭示的沉降区触点128的大功率垂直NPN双极晶体管600。NPN双极晶体管600包含重掺杂的n-型发射极扩散区614、轻掺杂的p型基极扩散区(p-基极)104'和包括在重掺杂的n+层上被示出为衬底100的n-型epi层150的n-型集电极扩散区。重掺杂的集电极提供低电阻，用于处理大电流。沉降区触点128通过相对较轻掺杂的epi层150提供低电阻路径，显著提高了NPN双极晶体管600的性能。接触插塞608通过PMD层118提供电连接到发射极614。接触插塞610接触提供与p-基极104'电接触的重掺杂的p-型扩散区114。
实例
以下具体实例进一步说明了所揭示的实施例，所述实例不应被解释为以任何方式限制本公开的范围或内容。
在n+衬底上厚度为约5μm的epi层上形成实例功率NMOS晶体管，epi层和衬底均包括硅。通过沉降区触点(CT)光刻法/蚀刻/光致抗蚀剂移除形成具有周长(CD>3.5um)的沉降区触点以形成内凹深度(硅中的深度)为约5.2μm的沉降区沟槽。屏障金属内衬128a包括Ti和TiN。金属填充材料128b包括作为W-CVD的7kA W，其仅部分地填充沉降区沟槽。电介质填料层128c沉积包括使用TEOS沉积工艺形成的5.5kA内衬电介质，接着是厚度为约2μm的液体SOG涂层，接着是固化SOG(在400℃下持续40分钟)以提供烧结SOG。氧化物CMP，然后内腐蚀W金属填充材料128b，并且最后铝互连沉积，并且接着是图案化。
虽然针对高功率半导体装置说明了所揭示的低电阻沉降区触点，但是这种低电阻沉降区触点可以形成于在可以得益于小面积的低电阻沉降区的任何类型的半导体装置/IC上。例如，减小接触电阻的常用方法是形成到扩散区的多个触点或触点阵列。有时，增加扩散区面积以容纳多个触点。相比于多个典型触点的阵列，一种所揭示的低电阻沉降区触点通常可以提供更低的电阻。除了较低的接触电阻外，所揭示的沉降区触点使得能够形成面积较小的扩散区，面积较小的扩散区还通过减小二极管电容而有益于电路性能。
所揭示的实施例可以用于形成半导体管芯，所述半导体管芯包含可以集成到各种组装流中以形成各种不同的装置和相关产品的分立的管芯或IC管芯。半导体管芯可以包含其中的各种元件和/或其上的层，包含屏障层、电介质层、装置结构、有源元件和无源元件，所述无源元件包含源极区域、漏极区域、位线、基极、发射极、集电极、导电线、导电孔等。此外，可以从包含双极、绝缘栅双极型晶体管(IGBT)、CMOS、BiCMOS和MEMS的各种工艺中形成半导体管芯。
本公开涉及的领域的技术人员应理解，在本发明权利要求书范围内的许多其它实施例和实施例的变体是可能的，并且可以在不脱离本公开的范围的情况下进行进一步的添加、删除、替换和修改。

Claims (33)

1.一种形成包含功率半导体装置的集成电路IC的方法，其包括：
提供衬底，所述衬底在其上具有外延epi层，所述epi层具有被形成在所述epi层内且被金属前电介质PMD层覆盖的至少一个晶体管；
从接触开口蚀刻穿过所述PMD层和所述epi层的至少一部分，所述接触开口包括延伸到所述功率半导体装置的至少第一节点的沉降区沟槽；
沉积金属填充材料，其中所述金属填充材料覆盖所述沉降区沟槽的侧壁和底部，但未完全填充所述沉降区沟槽；
在所述金属填充材料上方沉积电介质填料层以填充所述沉降区沟槽；
移除所述电介质填料层的覆盖层区域，在所述覆盖层区域中的所述金属填充材料的表面上停止以形成沉降区触点，其中在所述移除所述电介质填料层的所述覆盖层区域后，所述电介质填料层的一部分保留在所述沉降区沟槽中，以及
形成图案化互连金属，以在所述互连金属与所述沉降区沟槽的所述侧壁上的所述金属填充材料之间提供连接。
2.根据权利要求1所述的方法，其中所述沉积所述金属填充材料包括钨W的化学气相沉积CVD。
3.根据权利要求1所述的方法，其中所述沉积所述电介质填料层包括旋涂玻璃SOG涂层。
4.根据权利要求1所述的方法，其中所述功率半导体装置包括金属氧化物半导体场效应晶体管MOSFET装置，并且其中所述第一节点包括漏极。
5.根据权利要求1所述的方法，其中所述功率半导体装置包括双极型装置，并且其中所述第一节点包括集电极。
6.根据权利要求1所述的方法，其进一步包括：在所述沉积所述金属填充材料之前，在所述沉降区沟槽中形成屏障金属内衬。
7.一种功率半导体装置，其包括：
衬底，其在其上具有外延epi层；
第一装置端子、阱内的第二装置端子以及包括掩埋式漏极和掩埋式集电极中的一者的第三装置端子；
沉降区触点，其包括填充的沉降区沟槽，所述沉降区沟槽延伸穿过金属前电介质层及所述epi层的至少一部分到达所述第三装置端子，
其中所述沉降区触点包括金属填充材料，所述金属填充材料覆盖所述沉降区沟槽的侧壁和底部，但未完全填充所述沉降区沟槽，以及
内部电介质填料层，其安置于用于填充所述沉降区沟槽的所述金属填充材料内部以使得所述金属填充材料安置于所述侧壁及所述内部电介质填料层之间。
8.根据权利要求7所述的功率半导体装置，其中所述金属填充材料包括钨W。
9.根据权利要求7所述的功率半导体装置，其中所述电介质填料层包括具有微孔隙度的烧结旋涂玻璃SOG涂层。
10.根据权利要求7所述的功率半导体装置，其中所述epi层的厚度为至少5μm，并且其中所述沉降区沟槽到达所述epi层与所述衬底之间的界面。
11.根据权利要求7所述的功率半导体装置，其中所述功率半导体装置包括金属氧化物半导体场效应晶体管MOSFET装置，并且其中所述第三装置端子包括所述掩埋式漏极。
12.根据权利要求7所述的功率半导体装置，其中所述功率半导体装置包括双极型装置，并且其中所述第三装置端子包括所述掩埋式集电极。
13.一种包含功率半导体装置的集成电路IC，其包括：
衬底，其在其上具有外延epi层；
所述功率半导体装置，其包含：
第一装置端子、阱内的第二装置端子以及包括掩埋式漏极和掩埋式集电极中的一个的第三装置端子；
沉降区触点，其包括填充的沉降区沟槽，所述沉降区沟槽延伸穿过金属前电介质层及所述epi层的至少一部分到达所述第三装置端子，
其中所述沉降区触点包括金属填充材料，所述金属填充材料包括钨W，所述金属填充材料覆盖所述沉降区沟槽的侧壁和底部，但未完全填充所述沉降区沟槽，以及
内部电介质填料层，其处于用于填充所述沉降区沟槽的所述金属填充材料内以使得所述金属填充材料的至少一部分安置于所述侧壁及所述内部电介质填料层之间。
14.根据权利要求13所述的IC，其中电介质填料层包括具有微孔隙度的烧结旋涂玻璃SOG涂层。
15.根据权利要求13所述的IC，其中所述epi层的厚度为至少5μm，并且所述沉降区沟槽到达所述epi层与所述衬底之间的界面。
16.根据权利要求13所述的IC，其中所述功率半导体装置包括金属氧化物半导体场效应晶体管MOSFET装置，并且其中所述第三装置端子包括所述掩埋式漏极。
17.根据权利要求13所述的IC，其中所述功率半导体装置包括双极型装置，并且其中所述第三装置端子包括集电极。
18.一种半导体装置，其包括：
半导体衬底，其具有第一表面；
电子装置，其形成在所述衬底上方且具有装置端子；
电介质层，其位于所述电子装置上方且具有顶表面；
触点，其包括：
开口，其从所述顶表面延伸进入所述半导体衬底并朝向所述装置端子；
电介质填料，其安置于所述开口内且终止在所述顶表面处；以及
含金属的层，其在所述开口的侧壁处接触所述电介质层及所述装置端子，且所述含金属的层安置于所述电介质填料及所述半导体衬底之间的开口内并在所述顶表面处终止；
其中所述含金属的层同时覆盖所述开口的侧壁及所述开口的底部。
19.根据权利要求18所述的半导体装置，其中所述含金属的层包括钨W、铜Cu、铂Pt、钯Pd或钛合金中的至少一者。
20.根据权利要求18所述的半导体装置，其中所述电介质填料包括旋涂玻璃涂层。
21.根据权利要求18所述的半导体装置，其中所述含金属的层导电地连接到所述装置端子。
22.根据权利要求18所述的半导体装置，其中所述装置端子包括重掺杂层，且所述开口通过外延epi层延伸至所述重掺杂层，所述epi层具有比所述重掺杂层低的掺杂浓度。
23.根据权利要求22所述的半导体装置，其中所述epi层的厚度为至少5μm，且所述开口的所述底部与所述epi层和所述重掺杂层之间的界面之间的距离为0.5μm至1μm。
24.根据权利要求18所述的半导体装置，其中：
所述半导体衬底包括第一导电类型的外延epi层，且所述装置端子为第一装置端子；
所述半导体装置包括第二装置端子，所述第二装置端子包括安置于所述epi层内的阱区中的具有所述第一导电类型的扩散区；以及
所述阱区具有与所述第一导电类型相反的第二导电类型。
25.根据权利要求24所述的半导体装置，其中所述第一导电类型为n型，且所述第二导电类型为p型。
26.根据权利要求24所述的半导体装置，其包括至少部分地形成在所述阱区中并且将所述第二装置端子与第三装置端子电隔离的电介质隔离结构。
27.根据权利要求26所述的半导体装置，其中所述含金属的层包括接触半导体材料并安置于所述金属填充材料与所述开口的所述侧壁和所述开口的所述底部之间的屏障金属内衬。
28.根据权利要求27所述的半导体装置，其中所述屏障金属内衬包括第一层氮化钛TiN和安置于所述第一层上方的第二层钛Ti，所述第一层及所述第二层经布置以堆叠。
29.根据权利要求18所述的半导体装置，其进一步包括接触所述电介质层、所述含金属的层及所述电介质填料的金属互连。
30.一种形成包含半导体装置的集成电路IC的方法，所述方法包括：
在安置于衬底上方的外延epi层形成晶体管；
在所述epi层上方形成金属前电介质层并覆盖所述晶体管；
蚀刻穿过所述金属前电介质层及所述epi层的至少一部分的接触开口，其中所述接触开口包括侧壁和底部，并且所述接触开口具有延伸穿过所述金属前电介质层的第一部分和延伸穿过所述epi层的至少一部分的第二部分；
在所述接触开口中沉积含金属的层，以使得所述含金属的层在所述接触开口的所述侧壁和所述底部接触所述epi层，但所述含金属的层并不完全填充所述接触开口的所述第二部分；
在所述接触开口内沉积电介质填料层，以使得所述含金属的层将所述电介质填料层与所述epi层隔离；以及
形成与所述接触开口中的所述含金属的层导电地连接并且覆盖所述电介质填料层的图案化互连金属，其中蚀刻穿过所述金属前电介质层及所述epi层的至少一部分的所述接触开口以形成所述接触开口包括，蚀刻所述接触开口以使得所述接触开口的所述第二部分完全延伸穿过所述epi层并进入所述衬底的一部分。
31.根据权利要求30所述的方法，其中在所述含金属的层上方沉积电介质填料层以填充所述接触开口包括移除所述电介质填料层的覆盖层区域以形成触点，其中移除所述覆盖层区域后，所述电介质填料层的一部分保留在所述接触开口中。
32.根据权利要求30所述的方法，其中所述电介质填料包括旋涂玻璃SOG。
33.一种半导体装置，其包括：
电子装置，其形成在半导体衬底内或形成在所述半导体衬底上方；
电介质层，其安置于所述电子装置上方；
金属引线，其安置于所述电介质层上方；
触点，其包括：
开口，其从所述金属引线朝向所述半导体衬底延伸；
含金属的层，其位于所述开口的侧壁处且接触所述金属引线；以及
电介质填料，其安置于所述含金属的层上的所述开口内且接触所述金属引线；
其中所述含金属的层同时覆盖所述开口的侧壁及所述开口的底部。
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US9865718B1 (en) 2018-01-09

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