CN102569297B - 制备准谐振变换器的单片igbt和二极管结构及方法 - Google Patents

制备准谐振变换器的单片igbt和二极管结构及方法 Download PDF

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CN102569297B
CN102569297B CN201110436059.1A CN201110436059A CN102569297B CN 102569297 B CN102569297 B CN 102569297B CN 201110436059 A CN201110436059 A CN 201110436059A CN 102569297 B CN102569297 B CN 102569297B
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diode
igbt
bipolar transistor
outer peripheral
conduction type
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CN102569297A (zh
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安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明提出了一种制备准谐振变换器的结构及方法，包括在半导体衬底上形成的半导体功率器件，该半导体功率器件还包括一个在半导体衬底外围附近的通道终止区，其中通道终止区还包括一个二极管的外围端，对应与外围端水平相对的二极管另一端，设置在半导体功率器件的有源区上。在本发明的一个实施例中，半导体功率器件是一个绝缘栅双极晶体管(IGBT)。

Description

制备准谐振变换器的单片IGBT和二极管结构及方法
技术领域
本发明主要关于半导体功率器件的结构及制造方法。更确切的说，本发明是关于制备准谐振变换器的新型结构和方法，通过将绝缘栅双极晶体管(IGBT)与横向二极管相结合，横向二极管作为单片结构和封装结构，无需共同封装单独的二极管晶片，并且无需特殊的晶圆背部处理。
背景技术
用于配置和制备准谐振变换器成为功率器件的传统工艺，仍然面临许多困难与局限。确切地说，依据行业标准，传统的谐振变换器通常含有一个绝缘栅双极晶体管(IGBT)1和一个共同封装的二极管2，如图1A所示。与金属氧化物半导体场效应晶体管(MOSFET)不同，IGBT器件没有本征体二极管。在器件底部的P-型集电极层5会阻止将要形成的体二极管传导，如图1B所示。由于需要将两个单独的晶片(IGBT和二极管)作为一个共同封装的部件集成并连接起来，增加了制备成本。此外，IGBT必须做得较小，以便在相同的封装引脚内能够容纳单独的二极管晶片。这增加了器件的电阻，降低了电流处理能力。
传统的准谐振变换器的一种可能的应用就是利用电感加热的电饭煲。在这种应用中，软恢复不是二极管必须具备的特性。不需要高性能的二极管；在IGBT接通之前，二极管仅需要传导一段很短的时间。
如图1C所示，已经研发出了反向传导IGBT，在IGBT晶片的背部附近形成有垂直二极管。P-型集电极层5中的N-型植入区6，形成从IGBT集电极到发射极的P-N结二极管，从器件的底部开始，到顶部与P-型本体(或发射极)区7会合。如图1C所示的带有反平行(反向传导)垂直二极管的IGBT，需要额外的背部处理，包括在背部形成一个掩膜，用于背部植入。这些额外的背部处理工艺，增加了制备成本，而且实施难度更大。在处理薄晶圆时，较薄晶圆的额外的背部处理也增加损坏晶圆的风险。另外，如图1C所示，带有反向传导垂直二极管结构，使得器件可能在接通时受到突然跳回。
因此，仍然需要研发一种新型的IGBT结构以及封装结构，以解决本领域的技术人员在功率器件设计和制备领域中遇到的难题和局限。
发明内容
本发明的目的是提供一种制备准谐振变换器的新型结构和方法，通过将绝缘栅双极晶体管(IGBT)与横向二极管相结合，使横向二极管作为单片结构和封装结构，无需共同封装单独的二极管晶片，并且无需特殊的晶圆背部处理，以解决本领域的技术人员在功率器件设计和制备领域中遇到的难题和局限。
因此，本发明的一个方面在于，提出了一种新型和改良的器件结构及制备方法，制备与横向二极管结构相结合的单片IGBT，无需将IGBT晶片与单独的二极管晶片共同封装，并且无需为了制备反平行二极管在晶圆上进行背部处理工艺。从而改善了准谐振变换器的制备成本以及制备系数。
本发明的另一个方面在于，提出了一种新型和改良的器件结构及制备方法，制备与横向二极管结构相结合的单片IGBT，利用IGBT器件的通道终止区，形成横向二极管，从而在IGBT接通时，避免突然跳回问题。
本发明的另一个方面在于，提出了一种新型和改良的器件结构及制备方法，制备与横向二极管结构相结合的单片IGBT，作为P-i-N二极管，从而可以分别控制P-i-N二极管两边的注入效率，获得很低的反向恢复电荷Qrr，无需传统的寿命控制过程(例如电子辐照(ER)或金和铂扩散，形成很深的能级重组位置)。
本发明的另一个方面在于，提出了一种新型和改良的器件结构及制备方法，制备与横向二极管结构相结合的单片IGBT，利用IGBT器件的通道终止区，形成一个横向二极管，从而可以配置较大的IGBT晶片，并且/或者由于不需要共同封装单独的二极管晶片，因此可以使用较小的封装尺寸。
本发明的较佳实施例主要提出了一种形成在半导体衬底中的垂直半导体功率器件。该垂直半导体功率器件还包括相应的横向二极管的外围端，以及设置在半导体功率器件有源区上，与外围端水平相对的二极管中心端。在进一步的实施例中，半导体器件还包括一个通道终止区，在半导体衬底的外围附近，其中外围端在通道终止区接触半导体衬底。在本发明的一个实施例中，半导体功率器件是绝缘栅双极晶体管(IGBT)。
此外，本发明提出了一种在半导体衬底中制备垂直半导体功率器件的方法。该方法包括在半导体器件的截止区中形成外围端，并形成一个中心端设置在半导体功率器件的有源区中的，以便沿半导体衬底的整个水平方向形成一个横向二极管。为传播电场(例如浮动保护环)的截止结构，可以设置在有源区和外围端之间。该方法还包括在引线框的晶片垫上方组装半导体器件，并将二极管的外围端通过带有导电互联结构的引线框，连接到半导体器件的底端。
阅读以下详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将显而易见。
附图说明
图1A所示的俯视图表示传统技术中一种与肖特基二极管晶片共同封装的IGBT晶片的封装布局。
图1B表示传统的IGBT的剖面图。
图1C表示传统的IGBT的剖面图，具有形成在其背部的反向传导二极管。
图2A表示本发明所述的单片IGBT和二极管结构的剖面图，其中将沟槽MOSFET和横向二极管相结合。
图2B所示的电路图，表示图2A所示的IGBT器件的等效电路图。
图2C表示本发明的一个可选实施例的剖面图。
图2D表示本发明的另一个可选实施例的剖面图。
图3所示的俯视图，用于表示图2A所示的IGBT器件的封装布局。
图4A至4F所示的剖面图，表示用于制备图2A所示的IGBT器件的工艺。
图5A至5D所示的剖面图，表示用于制备类似于图2A所示的IGBT器件的工艺。
具体实施方式
图2A所示的剖面图表示本发明所述的与横向二极管结构集成的垂直绝缘栅双极晶体管(IGBT)，作为IGBT晶片100。作为示例，IGBT可以含有带有横向二极管的沟槽金属氧化物半导体(MOS)栅极。与横向二极管相结合的沟槽MOS结构，形成在半导体衬底中，集电极端101连接到P-型集电极层103下方的背部表面，P-型集电极层103设置在衬底底部。衬底包括一个N-型层，位于P-型集电极103上方；作为示例，如图2A所示，这个N-型层包括一个N-型场栏层105，位于P-型集电极103上方，以及一个轻掺杂的N-型层110(例如N-型外延层)，位于N-型场栏层105上方。N-型缓冲层105比N-型层110更加重掺杂。与横向二极管相结合的IGBT还包括一个沟槽栅极120，垫有栅极绝缘层115，覆盖在沟槽的侧壁和底面上方。沟槽栅极120在P-型本体区125(即发射极区)附近，包围着N+源极区130，紧邻外延层110顶面附近的栅极。
IGBT晶片100还包括一个有源区190和一个截止区195。集成的横向二极管从有源区190开始，水平延伸到截止区195。源极/本体/阳极接触沟槽也形成在外延层110中，发射极/阳极端170形成在第一导电插头140(例如钨)上方，轻掺杂的P-型区145形成在金属插头140下方。发射极/阳极端170(通过钨插头140)接触源极130和本体区125。本体区125可以补充轻掺杂的P-型区145以及重掺杂的P+本体接触区155。轻掺杂的P-型区145构成低注入效率的P-N二极管，带有外延层110和N-型区130’。二极管可以看成是P-i-N(P-型-本征-N-型)二极管，P-型区145作为二极管的阳极，轻掺杂的N-型区110作为二极管的本征部分，N-型区130’作为二极管的阴极。阴极端180形成在第二钨金属插头150上方，轻掺杂P-型区145形成在金属插头150下方，金属插头150设置在截止区195外围的半导体衬底的周围附近。截止区195还包括一个可选的截止结构(例如P-型保护环)160。截止结构160用于将截止电场在触及晶片边缘之前，横向扩展至整个截止区195。二极管阴极180可以在截止结构160的外围。P+区155和155’还形成在钨插头140和150附近，钨插头140和150在有源区190中的源极区130下方，N-型区130’在阴极端180下方的钨插头150附近。作为示例，N-型区130’可以是一个通道终止区，位于IGBT晶片100的外围附近。绝缘层165可以在发射极/阳极端170和阴极端180之间延伸，覆盖着钨插头140和钨插头150之间的外延层110的顶面。结合的横向二极管作为受控的反向恢复(即受控的反向恢复电荷(Qrr))二极管，无需传统的寿命控制方法。图2A所示的二极管为低注入效率的P-N结二极管，形成于接触沟槽下方的轻掺杂的P-型区145，以及N-型外延层110，然后穿过N-外延层145，到达阴极端180。此外，重掺杂的P+本体接触区155的尺寸很小，限制了从本体区注入的载流子的量。即使二极管的P-N结是垂直形成的，二极管阴极端180位于截止区195中，横向远离有源区190中的二极管阳极端170，因此可以认为该二极管是一个横向二极管。重掺杂的N-型区130’可以与源极区130同时形成，并且可以为阴极钨插头150提供良好的接触。重掺杂的P-型区155’可以与P+本体接触区155同时形成，可以有助于控制来自N+区130’在二极管的阴极端的注入效率。也可以设计N-型区130’的尺寸，减少来自N+区130’的载流子注入。因此，该横向二极管与IGBT单片集成，无需图1C所示的传统结构中所需的进一步的背部处理。阴极端180和钨插头150可以作为二极管的外围端，阳极端170和钨插头140可以作为横向二极管的中心端。
该器件包括一个垂直的绝缘栅双极晶体管(IGBT)，其集电极端101设置在底部，发射极/阳极端170设置在钨插头140上方的顶面上。
图2B所示的电路图表示图2A的IGBT晶片100的等效电路图。IGBT 198与反平行二极管199连接在一起。图2B与图2A相比，IGBT 198位于IGBT晶片100的有源区190中，从发射极/阳极端170到集电极端101，形成的反平行二极管199从有源区190中的阳极/发射极端170到截止区195中的阴极端180。阴极端180可以内部或外部连接到集电极端101上。
图2C所示的剖面图表示IGBT晶片100’，除了包括一个导电直通半导体通孔(TSV)185，将二极管的阴极端180电连接到集电极端101之外，其他都与图2A所示的IGBT晶片100类似。作为示例，TSV 185可以包括绝缘侧壁。
图2D表示本发明的一个可选实施例的剖面图。IGBT晶片100”除了具有平面栅极171，而不是沟槽栅极120之外，其他都与图2A所示的IGBT晶片100类似。集成的横向二极管从阳极/发射极电极170，到N-型外延层110内的P-型本体区125，并横向穿入截止区195(例如在N-型区域130’中)的阴极电极180内。
图3所示的俯视图表示IGBT封装200的结构，单片IGBT以及引线框201上的横向二极管晶片100(与图2A中类似)，与栅极引线211相结合，连接到IGBT晶片100的栅极垫120-1上，阴极/集电极引线212连接到IGBT的阴极端180以及集成的横向二极管晶片100，发射极/阳极引线213连接到IGBT的发射极/阳极端170以及集成的横向二极管晶片100。作为示例，这些部分可以通过接合引线215、夹片或任意其他导电互联结构连接起来。由于晶片100直接安装在引线框201的晶片垫202上方，并且由于阴极/集电极引线连接在晶片垫202上，因此引线框201的阴极/集电极引线212在IGBT以及集成的横向二极管晶片100的底面，也直接连接到集电极端101上(图3没有表示出)。因此，晶片100的集电极端101以及阴极端180在外部连接在一起。
图4A至4F所示的剖面图表示与图2A所示相类似的横向二极管半导体晶片100的IGBT的制备工艺。图4A表示P-型集电极层103位于N-型缓冲层105下面，N-型层110(例如外延层)位于缓冲层105上方。在图4B中，具有栅极电极120和栅极电介质115的栅极沟槽结构，形成在N-外延层110的顶部。在图4C中，制备P-型本体区125(以及可选浮动保护环160)以及N-型源极区130和N-型区130’。作为示例，源极区130和N-型区130’可以在同一个植入工艺中制备，P-型本体区125以及P-型浮动环160可以在同一个植入工艺中制备。绝缘层165(例如含有硼酸的硅玻璃(BPSG))形成在晶片的顶部上方。形成BPSG 165的图案，接触沟槽141和151部分形成在N-外延层110内，刻蚀到源极区130和本体区125中。重掺杂的P+本体接触区155和155’形成(例如植入和扩散)在部分刻蚀的接触沟槽141和151底部，如图4D所示。然后，进一步向下刻蚀部分刻蚀的接触沟槽141和151，以便穿过绝大部分的P+本体接触区155垂直刻蚀，触及轻掺杂的N-型外延层110。在接触沟槽的边缘处，仅保留一小部分的重掺杂P+本体接触区155。在这种情况下，轻掺杂的P-型区145可以形成(例如植入)在接触沟槽141和151的底部，以制备器件的低注入效率的P-N二极管，如图4E所示。导电插头(例如钨)140和150填充接触沟槽，制备一个金属层并形成图案，以制备发射极/阳极电极170以及阴极电极180。集电极101形成在器件的背面，接触集电极层103，如图4F所示。
图5A-5D所示的剖面图表示制备IGBT晶片100的可选工艺，从一种不同的半导体衬底装置开始。在图5A中，初始的半导体衬底相对较厚，轻掺杂层104位于N-型缓冲层105下方，轻掺杂N-型层(例如外延层)110位于N-型缓冲层105上方。进行上述图4B-4F所述的正面处理工艺，完成器件的正面，如图5B所示；但是，集电极端101还没有在背面形成。反而背部研磨相对较厚的轻掺杂层104，以形成一个很薄的轻掺杂层104’，如图5C所示。然后，大量的P-型植入在器件底部形成P-型集电极层103，随后形成集电极端101，如图5D所示。还可选择，进行背部研磨以及接下来的集电极植入，使工艺的最后不保留很薄的轻掺杂层104’(即没有轻掺杂区104’在中间，P-型集电极区103直接接触N-型缓冲层105)。
尽管本发明已经详细说明了现有的较佳实施例，但应理解这些说明不应作为本发明的局限。本领域的技术人员阅读上述详细说明后，各种变化和修正无疑将显而易见。例如，尽管上述内容说明的是n-通道IGBT器件，但是通过转换半导体区域的导电类型(例如从N-型转换成P-型，反之亦然)，本发明也可应用于P-通道器件。因此，应认为所附的权利要求书涵盖本发明的真实意图和范围内的全部变化和修正。

Claims (15)

1.一种半导体器件结构，其特征在于，包含：
一个形成在半导体衬底中的垂直半导体器件；
一个位于垂直半导体器件的截止区中的二极管的外围端；
一个设置在垂直半导体器件的有源区中的二极管的中心端，其横向远离所述二极管的外围端；
其中，所述二极管的外围端还包含一个导电插头，填充在半导体衬底外围附近的外围沟槽中，并且被设置在导电插头上方的阴极金属接头覆盖，其中所述的外围沟槽接触一个第一导电类型的上部掺杂区形成所述二极管的阴极区；
所述二极管的中心端还包含另一个导电插头，其填充在半导体衬底有源区中的中心接触沟槽中，电接触中心接触沟槽底部的第二导电类型的掺杂区，所述中心接触沟槽底部的第二导电类型的掺杂区形成所述二极管的阳极区。
2.如权利要求1所述的半导体器件结构，其特征在于，
所述的第一导电类型的上部掺杂区形成垂直半导体器件的一个通道终止区，位于半导体衬底外围附近的垂直半导体器件的截止区中，所述二极管的外围端在通道终止区接触半导体衬底。
3.如权利要求1所述的半导体器件结构，其特征在于，
所述的垂直半导体器件是一个与二极管集成的垂直绝缘栅双极晶体管(IGBT)，所述二极管设置在水平方向上，从垂直绝缘栅双极晶体管(IGBT)的有源区到截止区。
4.如权利要求1所述的半导体器件结构，其特征在于，还包含：
一个电场传播截止结构，设置在所述的垂直半导体器件的有源区和所述的二极管的外围端之间的所述的垂直半导体器件的截止区中。
5.如权利要求1所述的半导体器件结构，其特征在于：
所述中心端的导电插头被设置在这个中心端的导电插头上方的中心金属接头覆盖。
6.如权利要求1所述的半导体器件结构，其特征在于：
所述的垂直半导体器件是一个与二极管相结合的垂直绝缘栅双极晶体管(IGBT)，所述的二极管在水平方向上设置，从垂直绝缘栅双极晶体管(IGBT)的有源区横跨到截止区中的外围端，其中所述的垂直绝缘栅双极晶体管(IGBT)包含一个设置在半导体衬底底面上的集电极端，以及一个设置在半导体衬底顶面上的发射极端，其中发射极端是二极管的中心端。
7.如权利要求6所述的半导体器件结构，其特征在于：
所述的垂直绝缘栅双极晶体管(IGBT)形成在第一导电类型的第一半导体层中，并且垂直绝缘栅双极晶体管(IGBT)还包含一个在有源区中的栅极，所述的栅极在第二导电类型的本体区附近，本体区包围着第一导电类型的源极区，其中垂直绝缘栅双极晶体管(IGBT)还包含一个第二导电类型的集电极层，位于所述的第一半导体层下方。
8.如权利要求7所述的半导体器件结构，其特征在于，还包含：
一个第一导电类型的缓冲层，位于集电极层和第一半导体层之间，其中缓冲层比第一半导体层掺杂浓度更高。
9.如权利要求6所述的半导体器件结构，其特征在于，还包含：
一个设置在第一半导体层中的截止结构，位于垂直绝缘栅双极晶体管(IGBT)的有源区和所述二极管的外围端之间。
10.一种半导体器件结构，其特征在于，包含：
一个形成在半导体衬底中的垂直半导体器件；
一个位于垂直半导体器件的截止区中的二极管的外围端，其中，所述二极管的外围端还包含一个导电插头，填充在半导体衬底外围附近的外围沟槽中，接触一个第一导电类型的掺杂区，所述第一导电类型的掺杂区形成所述二极管的阴极区；
一个沉积在垂直半导体器件的有源区中的二极管的中心端，其横向远离所述二极管的外围端；
其中，所述的垂直半导体器件是一个与二极管相结合的垂直绝缘栅双极晶体管(IGBT)，所述的垂直绝缘栅双极晶体管(IGBT)形成在第一导电类型的第一半导体层中，并且垂直绝缘栅双极晶体管(IGBT)还包含一个在有源区中的栅极，所述的栅极在第二导电类型的本体区附近，本体区包围着第一导电类型的源极区，其中垂直绝缘栅双极晶体管(IGBT)还包含一个第二导电类型的集电极层，位于所述的第一半导体层下方；
其中，所述二极管的中心端还包含另一个导电插头，填充在中心沟槽中，接触垂直绝缘栅双极晶体管(IGBT)所述的本体区和源极区，并且被设置在中心端的导电插头上方的发射极/阳极金属接头覆盖；并且
一个第二导电类型的轻掺杂区设置在所述第一半导体层中，紧靠着中心沟槽的底面下方，形成所述二极管的阳极区，使二极管成为低注入效率的二极管。
11.如权利要求10所述的半导体器件结构，其特征在于，还包含：
一个穿过半导体衬底打开的导电通孔，作为一个直通半导体通孔(TSV)，将所述二极管的外围端内部连接到集电极端。
12.如权利要求10所述的半导体器件结构，其特征在于，还包含：
一个通道终止区，位于半导体衬底外围附近的半导体器件的截止区中，其中所述二极管的外围端在通道终止区接触半导体衬底。
13.一种用于垂直半导体器件的封装结构，其特征在于，其中：
所述的垂直半导体器件形成在半导体衬底中，在垂直半导体器件的截止区中具有一个横向二极管的外围端，在外围端的横向对面具有一个横向二极管的中心端，中心端设置在垂直半导体器件的有源区上；
引线框通过导电互联结构连接到所述的横向二极管的外围端和中心端以及所述的垂直半导体器件上；
其中，所述二极管的外围端还包含一个导电插头，填充在半导体衬底外围附近的外围沟槽中，接触一个第一导电类型的掺杂区形成所述二极管的阴极；所述二极管的中心端还包含另一个导电插头，其填充在半导体衬底有源区中的中心接触沟槽中，电接触中心接触沟槽底部的第二导电类型的掺杂区形成所述二极管的阳极。
14.如权利要求13所述的封装结构，其特征在于：
所述的垂直半导体器件是一个垂直绝缘栅双极晶体管(IGBT)，其与从垂直绝缘栅双极晶体管(IGBT)的有源区到截止区横向设置的横向二极管相结合，其中所述的垂直绝缘栅双极晶体管(IGBT)包含一个设置在半导体衬底底面上的集电极端，以及一个设置在半导体衬底顶面上的发射极端；
所述的引线框包含一个晶片垫，用于支撑半导体衬底的底面，并且接触所述的垂直绝缘栅双极晶体管(IGBT)的集电极端。
15.如权利要求14所述的封装结构，其特征在于，还包含：
一个导电互联结构，通过晶片垫，将横向二极管所述的外围端电连接到垂直绝缘栅双极晶体管(IGBT)的集电极端。
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