JP3625268B2 - 半導体装置の実装方法 - Google Patents

半導体装置の実装方法 Download PDF

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Publication number
JP3625268B2
JP3625268B2 JP2000046621A JP2000046621A JP3625268B2 JP 3625268 B2 JP3625268 B2 JP 3625268B2 JP 2000046621 A JP2000046621 A JP 2000046621A JP 2000046621 A JP2000046621 A JP 2000046621A JP 3625268 B2 JP3625268 B2 JP 3625268B2
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JP
Japan
Prior art keywords
semiconductor device
mounting
conductive adhesive
stud bump
rigid plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000046621A
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English (en)
Japanese (ja)
Other versions
JP2001237274A (ja
JP2001237274A5 (enExample
Inventor
伸介 中城
正徳 小野寺
雅光 生雲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
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Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2000046621A priority Critical patent/JP3625268B2/ja
Priority to US09/653,334 priority patent/US6420213B1/en
Priority to TW089118006A priority patent/TW455966B/zh
Priority to KR1020000054278A priority patent/KR100581246B1/ko
Publication of JP2001237274A publication Critical patent/JP2001237274A/ja
Publication of JP2001237274A5 publication Critical patent/JP2001237274A5/ja
Application granted granted Critical
Publication of JP3625268B2 publication Critical patent/JP3625268B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H10W74/019—
    • H10W72/071—
    • H10P72/74—
    • H10W72/00—
    • H10W72/013—
    • H10W74/012—
    • H10W74/15—
    • H10P72/7428—
    • H10W46/301—
    • H10W46/603—
    • H10W72/01215—
    • H10W72/01225—
    • H10W72/072—
    • H10W72/073—
    • H10W72/07338—
    • H10W72/251—
    • H10W72/252—
    • H10W72/354—
    • H10W72/856—
    • H10W90/724—
    • H10W90/734—

Landscapes

  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2000046621A 2000-02-23 2000-02-23 半導体装置の実装方法 Expired - Fee Related JP3625268B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000046621A JP3625268B2 (ja) 2000-02-23 2000-02-23 半導体装置の実装方法
US09/653,334 US6420213B1 (en) 2000-02-23 2000-08-31 Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive
TW089118006A TW455966B (en) 2000-02-23 2000-09-02 Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive
KR1020000054278A KR100581246B1 (ko) 2000-02-23 2000-09-15 반도체 장치의 실장 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000046621A JP3625268B2 (ja) 2000-02-23 2000-02-23 半導体装置の実装方法

Publications (3)

Publication Number Publication Date
JP2001237274A JP2001237274A (ja) 2001-08-31
JP2001237274A5 JP2001237274A5 (enExample) 2004-12-02
JP3625268B2 true JP3625268B2 (ja) 2005-03-02

Family

ID=18569002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000046621A Expired - Fee Related JP3625268B2 (ja) 2000-02-23 2000-02-23 半導体装置の実装方法

Country Status (4)

Country Link
US (1) US6420213B1 (enExample)
JP (1) JP3625268B2 (enExample)
KR (1) KR100581246B1 (enExample)
TW (1) TW455966B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313841A (ja) * 2000-04-14 2002-10-25 Namics Corp フリップチップ実装方法
US6461881B1 (en) * 2000-06-08 2002-10-08 Micron Technology, Inc. Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
DE10063907A1 (de) * 2000-12-21 2002-07-04 Philips Corp Intellectual Pty Detektor zum Detektieren von elektromagnetischer Strahlung
US6780682B2 (en) * 2001-02-27 2004-08-24 Chippac, Inc. Process for precise encapsulation of flip chip interconnects
JP2002299595A (ja) * 2001-04-03 2002-10-11 Matsushita Electric Ind Co Ltd 固体撮像装置およびその製造方法
JP4663184B2 (ja) * 2001-09-26 2011-03-30 パナソニック株式会社 半導体装置の製造方法
JP3717899B2 (ja) 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2004079951A (ja) * 2002-08-22 2004-03-11 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US20060057763A1 (en) * 2004-09-14 2006-03-16 Agency For Science, Technology And Research Method of forming a surface mountable IC and its assembly
JP5029597B2 (ja) 2006-02-13 2012-09-19 パナソニック株式会社 カード型記録媒体およびカード型記録媒体の製造方法
JP2008218643A (ja) * 2007-03-02 2008-09-18 Fujitsu Ltd 半導体装置及びその製造方法
US7951648B2 (en) * 2008-07-01 2011-05-31 International Business Machines Corporation Chip-level underfill method of manufacture
TWI478257B (zh) * 2009-08-06 2015-03-21 宏達國際電子股份有限公司 封裝結構及封裝製程
CN101989554B (zh) * 2009-08-06 2012-08-29 宏达国际电子股份有限公司 封装结构及封装工艺
TWI430376B (zh) * 2011-02-25 2014-03-11 聯測科技股份有限公司 The Method of Fabrication of Semiconductor Packaging Structure
CN110854057B (zh) * 2019-11-14 2022-07-12 京东方科技集团股份有限公司 一种转移基板及其制作方法、转移方法
WO2022032523A1 (zh) * 2020-08-12 2022-02-17 重庆康佳光电技术研究院有限公司 芯片转移方法以及显示装置
CN117690810A (zh) * 2023-12-11 2024-03-12 安徽丰芯半导体有限公司 一种保证芯片贴合均匀度的芯片覆晶工艺

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030308A (en) * 1986-07-14 1991-07-09 National Starch And Chemical Investment Holding Corporation Method of bonding a semiconductor chip to a substrate
US5926694A (en) * 1996-07-11 1999-07-20 Pfu Limited Semiconductor device and a manufacturing method thereof
JPH10189663A (ja) 1996-12-26 1998-07-21 Shibuya Kogyo Co Ltd ボンディング装置
AU8502798A (en) * 1997-07-21 1999-02-10 Aguila Technologies, Inc. Semiconductor flip-chip package and method for the fabrication thereof
US6063647A (en) * 1997-12-08 2000-05-16 3M Innovative Properties Company Method for making circuit elements for a z-axis interconnect

Also Published As

Publication number Publication date
TW455966B (en) 2001-09-21
US6420213B1 (en) 2002-07-16
KR100581246B1 (ko) 2006-05-22
JP2001237274A (ja) 2001-08-31
KR20010085224A (ko) 2001-09-07

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