WO2007094167A1 - 回路基板および回路基板の製造方法 - Google Patents

回路基板および回路基板の製造方法 Download PDF

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Publication number
WO2007094167A1
WO2007094167A1 PCT/JP2007/051542 JP2007051542W WO2007094167A1 WO 2007094167 A1 WO2007094167 A1 WO 2007094167A1 JP 2007051542 W JP2007051542 W JP 2007051542W WO 2007094167 A1 WO2007094167 A1 WO 2007094167A1
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WIPO (PCT)
Prior art keywords
wiring board
electronic component
circuit board
bumps
chip
Prior art date
Application number
PCT/JP2007/051542
Other languages
English (en)
French (fr)
Inventor
Hidenobu Nishikawa
Daido Komyoji
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to CN2007800052184A priority Critical patent/CN101385402B/zh
Priority to JP2008500433A priority patent/JP5029597B2/ja
Priority to US12/161,907 priority patent/US8291582B2/en
Publication of WO2007094167A1 publication Critical patent/WO2007094167A1/ja
Priority to US13/614,630 priority patent/US8866021B2/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • the present invention relates to a circuit board in which electronic components are mounted on a flexible wiring board and a method for manufacturing the circuit board.
  • a method of manufacturing a circuit board by mounting electronic components on a wiring board a method of providing bumps on the electrodes of the electronic parts and bonding the bumps to the electrodes on the wiring board is known. It has been. For example, there is a method in which a conductive adhesive is transferred onto an electrical connection contact (bump) of a semiconductor chip by a stamping method, and the conductive adhesive is heated and cured while pressing the semiconductor chip against a circuit board. It has been proposed (for example, see Patent Document 1).
  • an IC card (Integrated Circuit Card) has been widely used as a card-type recording medium replacing a magnetic card.
  • a method for mounting a bare chip on a substrate for an IC card a method of flip chip mounting a bare chip having a gold bump via an anisotropic conductive film is proposed (for example, Patent Document 2). reference).
  • a technology has been proposed in which the tip of a bump electrode (bump) of an electronic component is inserted into the electrode of a substrate for an IC card, and the electronic component on the substrate is sealed with a thermoplastic resin (for example, And Patent Document 3).
  • a wiring board made of PE ⁇ polyethylene terephthalate
  • PET polyethylene terephthalate
  • the wiring board made of PET is highly flexible, when an electronic component is mounted on the wiring board, the wiring board in the vicinity of the area where the bump is pressed is distorted and deformed. For this reason, The lower surface of the electronic component and the upper surface of the wiring board are close to each other in the vicinity of the die and near the center between the bumps.
  • Patent Document 1 Japanese Patent Publication No. 7-50726
  • Patent Document 2 Japanese Patent Laid-Open No. 11-175682
  • Patent Document 3 Japanese Patent Laid-Open No. 2005-111928
  • a method for manufacturing a circuit board according to the present invention includes: a) applying an anisotropic conductive resin containing conductive particles only to a plurality of bumps of an electronic component; and b) via the anisotropic conductive resin. C) placing electronic components on the main surface of the flexible wiring board; and c) pressing the electronic components against the wiring board to cure the anisotropic conductive resin applied to the plurality of bumps, Bonding the bump to the wiring of the wiring board.
  • the anisotropic conductive resin is imparted only to the plurality of bumps, so that it is possible to manufacture a circuit board that prevents mounting defects of electronic components.
  • the circuit board of the present invention includes a flexible wiring board, an electronic component mounted on the main surface of the wiring board via a plurality of bumps, and an anisotropic conductive material including conductive particles.
  • a first resin layer formed of a resin and individually covering a plurality of bumps, and a second resin layer for fixing the electronic component and the wiring board are provided.
  • FIG. 1 is a plan view showing a configuration of a circuit board according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a part of the circuit board according to the embodiment of the present invention cut at the position of line 2-2 in FIG.
  • FIG. 3 is a flowchart showing the flow of manufacturing a circuit board according to an embodiment of the present invention.
  • FIG. 4A is a partial cross-sectional view for explaining the circuit board manufacturing method according to the embodiment of the present invention.
  • FIG. 4B is a partial cross-sectional view illustrating the method for manufacturing the circuit board according to the embodiment of the present invention.
  • FIG. 4C is a partial cross-sectional view illustrating the method of manufacturing the circuit board according to the embodiment of the present invention.
  • FIG. 4D is a partial cross-sectional view illustrating the method for manufacturing the circuit board according to the embodiment of the present invention.
  • FIG. 1 is a plan view showing a configuration of a circuit board 1 according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view showing a part of the circuit board 1 cut at the position of line 2-2 in FIG. .
  • the circuit board 1 is, for example, an inlet for an IC card (Integrated Circuit Card).
  • the circuit board 1 has a flexible wiring board 2 having a force such as PET, and one main surface (the upper main surface in FIG. 2, hereinafter referred to as “upper surface”) 2 1
  • an electronic component such as an IC chip (hereinafter referred to as “IC chip”) 3 to be mounted 3 and an antenna 22 for transmitting and receiving information and power are provided.
  • the wiring board 2 is mounted in a state of being sandwiched in the vicinity of the junction with the IC chip 3.
  • the IC chip 3 shown in FIGS. 1 and 2 is a storage element for storing predetermined information such as product history and management data, for example, FeR AM (Ferroelectric Random Access Memory ) Etc.
  • the chip body 31 of the IC chip 3 is substantially rectangular in plan view, and is provided on an electrode 32 of a surface (hereinafter referred to as “lower surface”) 311 of the chip body 31 facing the wiring board 2.
  • a plurality of bumps 33 are provided. Then, the IC chip 3 is mounted on the upper surface 21 of the wiring board 2 via the bumps 33.
  • the bump 33 is, for example, a bowl-shaped ball bump (so-called stud bump) having a protrusion 331 at the tip.
  • the radio communication antenna 22 formed in a coil shape along the outer periphery of the wiring board 2 constitutes the antenna 22 formed on the upper surface 21 of the wiring board 2. It is electrically connected to the IC chip 3 via two electrodes 23 that are part of the wiring, and reads information stored in the IC chip 3.
  • the two bumps 33 located on the left side in FIG. 1 are electrically connected to the two electrodes 23 on the wiring board 2, respectively.
  • the bump 33 located on the right side in FIG. 1 is, for example, a dummy bump for stably mounting the IC chip 3, and is not electrically connected to the wiring board 2 in this case.
  • the circuit board 1 includes a plurality of first resin layers 4 that individually cover the plurality of bumps 33 inside the edge of the chip body 31 of the IC chip 3.
  • the first resin layer 4 is formed of, for example, an anisotropic conductive resin containing fine conductive particles. ing.
  • the circuit board 1 covers the plurality of first resin layers 4 between at least the upper surface 21 of the wiring board 2 and the lower surface 311 of the IC chip 3 and the IC chip 3.
  • the second resin layer 5 is attached to the wiring board 2.
  • the second resin layer 5 is formed of, for example, an adhesive that is a non-conductive resin. In FIG. 1, the second resin layer 5 is not shown for easy understanding.
  • the thickness of the wiring board 2 is about 12.5 ⁇ m in the present embodiment, which is preferably 5 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the IC chip 3 is, for example, about 50 ⁇ m, and the height of the bump 33 is about 25 ⁇ m. If the thickness of the wiring board 2 is less than 5 ⁇ m, it is difficult to handle, and if it exceeds 50 m, it is difficult to realize a thin and flexible circuit board.
  • FIG. 3 is a flowchart showing the flow of manufacturing the circuit board 1 according to the embodiment of the present invention
  • FIGS. 4A to 4D are partial cross-sectional views for explaining the manufacturing method of the circuit board 1.
  • 4A to 4D are partial sectional views cut along the line 2-2 in FIG.
  • the IC chip 3 is held by the chip holding portion 91 of the mounting apparatus (not shown), and at least the protrusions 331 at the tips of the plurality of bumps 33 of the IC chip 3 are
  • the layered anisotropic conductive resin 40 formed on the member 42 having a predetermined smooth surface is brought into contact. Thereafter, the IC chip 3 is lifted upward, and the bumps 33 are separated from the layered anisotropic conductive resin 40.
  • anisotropic conductive resin 4a containing minute conductive particles is applied (that is, transferred) to at least protrusion 331 at the tip of bump 33 (step S11). .
  • bumps 33 are bonded on the upper surface 21 of the wiring board 2 in the region where the IC chip 3 is to be mounted (at least the region facing the lower surface of the IC chip).
  • An adhesive 5a such as a non-conductive resin paste is applied to a part of the region other than the region to be formed (the plurality of electrodes 23) (step S12).
  • the chip holding portion 91 is moved relatively above the wiring board 2 to adjust the position of the IC chip 3 with respect to the wiring board 2. (Step S13).
  • the two bumps 33 other than the dummy bumps face the two electrodes 23 that are part of the wiring of the wiring board 2.
  • the IC chip 3 is lowered together with the chip holding portion 91, and the anisotropic conductive conductive resin 4 a applied to the protrusion 331 at the tip of the bump 33 is interposed.
  • the IC chip 3 is placed on the upper surface 21 of the wiring board 2.
  • the adhesive 5a is spread and spread around the lower surface 311 of the chip body 31 by its own weight, and is filled between the IC chip 3 and the wiring board 2 (step S14). ).
  • the holding of the IC chip 3 by the chip holding portion 91 is released, and the IC chip 3 is pressed against the upper surface 21 of the wiring board 2 via the pressing tool 92.
  • the wiring board 2 is squeezed by the pressing force of the IC chip 3, and a portion near the bump 33 of the wiring board 2 is deformed downward, for example.
  • a peripheral portion slightly apart from the bump 33 of the circuit board 2 is deformed upward, for example, and is close to the lower surface 311 of the IC chip 3.
  • the wiring board 2 and the IC chip 3 are close to each other in the vicinity of the edge of the chip body 31 of the IC chip 3 and the center between the bumps 33 (near the center of a straight line connecting two adjacent bumps 33).
  • the anisotropic conductive resin 4 a is pushed and spread around the bumps 33 by the pressing of the IC chip 3, and the adhesive 5 a is further pushed.
  • step SI 1 the amount of anisotropic conductive resin 4 a applied to the protrusion 331 at the tip of the bump 33 is small. Therefore, the anisotropic conductive resin 4a spread by the bump 33 does not spread to the outside of the edge of the chip body 31 of the IC chip 3, and the vicinity of the bump 33 between the chip body 31 and the wiring board 2 Stay on.
  • the bump 33 and the electrode 23 are connected by pressure contact, and the conductive particles in the anisotropic conductive resin 4a are crushed and are electrically connected reliably.
  • the pressing tool 92 is pressed against the wiring board 2 by a heater (not shown) provided on the pressing tool 92. Heated through 92.
  • the anisotropic conductive resin 4a applied to the plurality of bumps 33 of the IC chip 3 is cured by heat.
  • a plurality of first resin layers 4 that individually cover the plurality of bumps 33 are formed inside the edge of the IC chip 3.
  • the IC chip 3 is electrically connected to the electrode 23 of the antenna 22 (see FIG. 1) of the wiring board 2 with the bump 33 interposed therebetween, and IC chip 3 is bonded to wiring board 2 and mounted.
  • the adhesive 5a is also cured by heat to form the second resin layer 5 that seals the space between the IC chip 3 and the wiring board 2, and the IC chip 3 is firmly fixed to the wiring board 2.
  • Step S15 As described above, the IC chip 3 is mounted on the wiring board 2 and the circuit board 1 is manufactured.
  • the main surfaces on both sides of the circuit board 1 are covered with a force bar sheet or the like formed of, for example, polycarbonate, and an IC card is manufactured.
  • the IC card is formed with a thickness of about 0.76 mm, for example.
  • a small amount of the anisotropic conductive resin 4a is applied to at least the protrusion 331 at the tip of the bump 33 of the IC chip 3. This prevents the conductive particles contained in the anisotropic conductive resin 4a from spreading outside the edge of the chip body 31 of the IC chip 3 and near the center between the bumps 33 when the IC chip 3 is mounted. it can. That is, the conductive particles can be selectively present only in the joint portion between the bump 33 and the wiring board 2 and in the vicinity of the joint portion.
  • circuit board 1 of the present embodiment it is possible to prevent the conductive particles from reaching the location where the distance between the upper surface 21 of the wiring board 2 and the lower surface 311 of the IC chip 3 is small. As a result, circuit board with excellent reliability such as short circuit of IC chip 3 is prevented by preventing conduction between wiring board 2 and chip body 31 and conduction between bumps 33 at that location. 1 can be realized.
  • the anisotropic conductive resin 4a applied to the plurality of bumps 33 causes the inner side of the edge of the IC chip 3 to reach the inner side.
  • a plurality of first resin layers 4 that individually cover the plurality of bumps 33 are formed. This prevents the anisotropic conductive resin 4a from reaching the edge of the IC chip 3 or the center between the bumps 33. As a result, it is possible to more reliably prevent the conductive particles from reaching that part, and to further prevent the occurrence of mounting defects of the IC chip 3.
  • the method of manufacturing the circuit board 1 according to the present embodiment is suitable for mounting electronic components such as the IC chip 3 on the wiring board 2 having a thickness of 5 m or more and 50 m or less, which is easy to stagnate.
  • the bump 33 of the IC chip 3 is brought into contact with the layered anisotropic conductive resin 40, and the anisotropic conductive resin 4 a is easily attached to the protrusion 331 of the bump 33. Therefore, the productivity of the circuit board 1 can be improved.
  • the bump 33 of the IC chip 3 is formed by a stud bump having a protrusion 331 at the tip, so that the anisotropic conductive resin 4a is surely sealed by the unevenness of the tip of the bump 33 and the bump 33 is sealed. Only the amount necessary for stopping can be attached and held.
  • the IC chip 3 is firmly fixed to the wiring board 2 by the second resin layer 5 and the space between the chip main body 31 and the wiring board 2 is sealed. 3 can be prevented more reliably and the reliability of the circuit board 1 can be further improved.
  • circuit board of the present embodiment it is not particularly necessary to perform the conduction preventing process by forming an insulating film or the like on the chip body 31 of the IC chip 3, so that the IC power can be reduced accordingly. The influence on the communication characteristics of the card can be prevented. Therefore, it is particularly suitable for circuit boards such as IC tag inlets that use wiring boards with antennas.
  • the bump 33 of the IC chip 3 is brought into contact with the layered anisotropic conductive resin 40, and the anisotropic conductive resin 4a is applied to the protrusion 331 at the tip.
  • anisotropic conductive resin 4a may be sequentially applied to the tip of each bump 33 with a dispenser or the like.
  • the present invention is not limited to this.
  • the adhesive 5a is applied so as to surround a plurality of regions where the plurality of bumps 33 are to be bonded among the regions where the IC chip 3 is mounted on the upper surface 21 of the wiring board 2.
  • a part of the adhesive 5a formed on the entire circumference is provided with a wrinkle portion that is not provided for air bleeding.
  • the force described using the IC card inlet as an example is not limited to this.
  • it may be applied to manufacture of an inlet such as an IC tag, and may be applied to mounting of a driver IC such as a display by a COF (chip on film) method.
  • the IC chip 3 such as a memory element is described as an example of the electronic component 3 mounted on the wiring board 2, but the present invention is not limited to this.
  • a mold type IC chip having bumps such as a chip size package (CSP) or a chip component that is a passive component may be mounted, or a plurality of electronic components may be mounted. .
  • CSP chip size package
  • the force described using PET as an example of the wiring board 2 is not limited to this.
  • it may be a flexible substrate made of PEEK (polyetheretherketone) or polyimide.
  • the present invention can be used for a circuit board used as an inlet of an IC card or an IC tag, and various other circuit boards.

Abstract

電子部品の複数のバンプのみに導電性粒子を含む異方導電性樹脂を付与するステップと、異方導電性樹脂を介して可撓性の配線基板の主面上に電子部品を配置するステップと、電子部品を配線基板に押圧して複数のバンプに付与された異方導電性樹脂を硬化させ、複数のバンプを配線基板の電極に接合するステップと、を含む。これにより、電子部品の実装不良を防止することができる。

Description

明 細 書
回路基板および回路基板の製造方法
技術分野
[0001] 本発明は、可撓性の配線基板に電子部品が実装された回路基板および回路基板 の製造方法に関する。
背景技術
[0002] 従来、配線基板に電子部品を実装して回路基板を製造する方法の 1つとして、電 子部品の電極上にバンプを設け、バンプと配線基板上の電極とを接合する方法が知 られている。例えば、半導体チップの電気的接続接点 (バンプ)上に導電性接着剤を スタンビング法等により転写し、半導体チップを回路基板に対して押圧しながら導電 性接着剤を加熱して硬化する方法が提案されている (例えば、特許文献 1参照)。
[0003] 一方、近年、磁気カードに代わるカード型記録媒体として ICカード (Integrated C ircuit Card)が普及してきている。そして、 ICカード用の基板上にベアチップを実 装する方法として、金バンプを有するベアチップを銀ペーストゃ異方導電性フィルム を介してフリップチップ実装する方法が提案されている（例えば、特許文献 2参照)。 さらに、電子部品の突起電極 (バンプ)の先端を ICカード用の基板の電極に食い込 ませて装着し、熱可塑性榭脂により基板上の電子部品を封止する技術が提案されて いる（例えば、特許文献 3参照)。
[0004] し力しながら、特許文献 1によれば、実装される電子部品が小型になるにしたがって 、バンプ間の距離が短くなる。そのため、銀ペーストのようにフィラー含有率が高い導 電性接着剤を介して電子部品を実装すると、バンプ間に導電性接着剤が広がり、電 極間の短絡等の実装不良を生じる場合がある。また、非導電性榭脂ペースト等を利 用した実装では、バンプと電極との電気的接続に対する信頼性向上に限界がある。
[0005] また、特許文献 2、 3に示されて 、る ICカードでは、薄型化やコスト低減のために PE τ (ポリエチレンテレフタラート)製の配線基板が一般的に利用されている。しかし、 P ET製の配線基板は可撓性が高いため、電子部品を配線基板に実装する場合、バン プが押圧される領域近傍の配線基板が橈んで変形する。そのため、電子部品のエツ ジ近傍やバンプ間の中央近傍において電子部品の下面と配線基板の上面とが近接 する。そのとき、例えば電子部品と配線基板との電気的接続に異方導電性榭脂を用 いた場合、電子部品と配線基板とが近接している箇所において、異方導電性榭脂に 含まれる導電性粒子が電子部品と配線基板との間に挟まれる。その結果、電子部品 と配線基板とが電気的に接続し、電子部品の実装不良を生じるなどの問題がある。 特許文献 1：特公平 7— 50726号公報
特許文献 2：特開平 11— 175682号公報
特許文献 3：特開 2005 - 111928号公報
発明の開示
[0006] 本発明の回路基板の製造方法は、 a)電子部品の複数のバンプのみに導電性粒子 を含む異方導電性榭脂を付与するステップと、 b)異方導電性榭脂を介して可撓性の 配線基板の主面上に電子部品を配置するステップと、 c)電子部品を配線基板に押 圧して複数のバンプに付与された異方導電性榭脂を硬化させ、複数のバンプを配線 基板の配線に接合するステップと、を含む。
[0007] この方法により、複数のバンプのみに異方導電性榭脂を付与するため、電子部品 の実装不良を防止した回路基板を作製できる。
[0008] また、本発明の回路基板は、可撓性の配線基板と、配線基板の主面上に複数のバ ンプを介して実装される電子部品と、導電性粒子を含む異方導電性榭脂により形成 され、複数のバンプを個別に覆う第 1榭脂層と、電子部品と配線基板を固定する第 2 樹脂層と、を備える。
[0009] この構成により、電子部品を配線基板に強固に固定し、接続の信頼性に優れた回 路基板を実現できる。
図面の簡単な説明
[0010] [図 1]図 1は、本発明の実施の形態に係る回路基板の構成を示す平面図である。
[図 2]図 2は、本発明の実施の形態に係る回路基板の図 1の 2— 2線の位置で切断し た一部を示す断面図である。
[図 3]図 3は、本発明の実施の形態に係る回路基板の製造の流れを示すフローチヤ ートである。 圆 4A]図 4Aは、本発明の実施の形態に係る回路基板の製造方法を説明する部分 断面図である。
園 4B]図 4Bは、本発明の実施の形態に係る回路基板の製造方法を説明する部分 断面図である。
圆 4C]図 4Cは、本発明の実施の形態に係る回路基板の製造方法を説明する部分 断面図である。
[図 4D]図 4Dは、本発明の実施の形態に係る回路基板の製造方法を説明する部分 断面図である。
符号の説明
1 回路基板
2 配線基板
3 ICチップ (電子部品）
4 第 1榭脂層
4a, 40 異方導電性榭月 1
5 第 2榭脂層
5a 接着剤
21 上面
22 アンテナ
23, 32 電極
31 チップ本体
33 ノ ンプ
42 部材
91 チップ保持部
92 押圧ツール
311 下面
331 突起部
発明を実施するための最良の形態
(実施の形態） 図 1は本発明の実施の形態に係る回路基板 1の構成を示す平面図であり、図 2は 回路基板 1を図 1の 2— 2線の位置で切断した一部を示す断面図である。
[0013] 図 1と図 2に示すように、回路基板 1は、例えば ICカード（Integrated Circuit Ca rd)用のインレットである。そして、回路基板 1は、例えば PETなど力もなる可撓性の 配線基板 2と、その一方の主面（図 2中の上側の主面であり、以下、「上面」と記す） 2 1上に実装される、例えば ICチップなどの電子部品（以下、「ICチップ」と記す） 3と、 情報や電力を送受するアンテナ 22を備える。このとき、一般的に、図 2に示すように、 配線基板 2が ICチップ 3との接合部近傍にぉ ヽて橈んだ状態で実装されて!ヽる。な お、図 2では橈みを強調して示している。ここで、図 1と図 2に示す ICチップ 3は、例え ば商品履歴や管理データ等の所定の情報を記憶する記憶素子であり、例えば FeR AM (Ferroelectric Random Access Memoryノ 丄 (Large scale I ntegration)などである。
[0014] また、 ICチップ 3のチップ本体 31は、平面視において略矩形であり、チップ本体 31 の配線基板 2と対向する面（以下、「下面」と記す） 311の電極 32上に設けられる複数 のバンプ 33を備えている。そして、 ICチップ 3はバンプ 33を介して配線基板 2の上面 21上に実装される。なお、バンプ 33は、図 2に示すように、その先端部に突起部 331 を有する、例えば鉅型のボールバンプ（いわゆる、スタッドバンプ）である。
[0015] また、図 1に示すように、配線基板 2の外周に沿ってコイル状に形成された無線通 信用のアンテナ 22は、配線基板 2の上面 21上に形成されたアンテナ 22を構成する 配線の一部である 2つの電極 23を介して ICチップ 3と電気的に接続され、 ICチップ 3 に記憶されている情報の読み取りを行うものである。そして、回路基板 1で、図 1中の 左側に位置する 2つのバンプ 33が、それぞれ配線基板 2上の 2つの電極 23と電気的 に接続される。また、図 1中の右側に位置するバンプ 33は、 ICチップ 3を安定して実 装するための、例えばダミーバンプであり、この場合、配線基板 2と電気的に接続さ れていない。
[0016] そして、図 1と図 2に示すように、回路基板 1は、 ICチップ 3のチップ本体 31のエッジ よりも内側において複数のバンプ 33を個別に覆う複数の第 1榭脂層 4を備える。なお 、第 1榭脂層 4は、例えば微小な導電性粒子を含む異方導電性榭脂などで形成され ている。
[0017] さらに、図 1に示すように、回路基板 1は、少なくとも配線基板 2の上面 21と ICチップ 3の下面 311との間に、複数の第 1榭脂層 4を覆うとともに ICチップ 3を配線基板 2と 接着する第 2榭脂層 5を備える。なお、第 2榭脂層 5は、例えば非導電性榭脂である 接着剤などで形成されている。また、図 1では、理解を容易にするために第 2榭脂層 5を図示していない。
[0018] ここで、配線基板 2の厚さは、 5 μ m以上 50 μ m以下が好ましぐ本実施の形態で は、約 12. 5 μ mとしている。また、 ICチップ 3の厚さは、例えば約 50 μ mであり、バン プ 33の高さは約 25 μ mである。なお、配線基板 2の厚みが 5 μ m未満では、取り扱 いが困難であり、 50 mを超える場合には、薄型化や可撓性を有する回路基板を実 現することが困難となる。
[0019] 以下に、本発明の実施の形態に係る回路基板 1の製造方法について、図 3を用い て説明する。図 3は本発明の実施の形態に係る回路基板 1の製造の流れを示すフロ 一チャートで、図 4Aから図 4Dは回路基板 1の製造方法を説明する部分断面図であ る。なお、図 4Aから図 4Dは、図 1中の 2— 2線の位置で切断した部分断面図で示し ている。
[0020] まず、図 4Aに示すように、実装装置（図示せず)のチップ保持部 91により ICチップ 3を保持し、少なくとも ICチップ 3の複数のバンプ 33の先端部の突起部 331を、所定 の平滑面を有する部材 42上に形成された層状の異方導電性榭脂 40に接触させる。 その後、 ICチップ 3を上方に持ち上げて、バンプ 33を層状の異方導電性榭脂 40から 離間させる。これにより、図 4Bに示すように、微小な導電性粒子を含む異方導電性 榭脂 4aが、少なくともバンプ 33の先端部の突起部 331に付与 (すなわち、転写)され る（ステップ S 11)。
[0021] 次に、図 4Bに示すように、配線基板 2の上面 21上で、 ICチップ 3が実装される予定 の領域 (少なくとも ICチップの下面と対向する領域)のうち、バンプ 33が接合される予 定の領域 (複数の電極 23)以外の領域の一部の領域に、例えば非導電性榭脂ぺ一 ストなどの接着剤 5aを付与する (ステップ S 12)。そして、チップ保持部 91を配線基板 2の上方へと相対的に移動させ、配線基板 2に対する ICチップ 3の位置の調整を行う (ステップ S13)。これにより、ダミーバンプ以外の 2つのバンプ 33が、配線基板 2の配 線の一部である 2つの電極 23とそれぞれ対向する。
[0022] 次に、図 4Cに示すように、 ICチップ 3をチップ保持部 91とともに下降させて、バン プ 33の先端部の突起部 331に付与された異方導電性榭脂 4aを介して ICチップ 3を 配線基板 2の上面 21上に配置する。このとき、接着剤 5aは、チップ本体 31の自重に より、チップ本体 31の下面 311で周囲に向けて押し広げられるとともに、 ICチップ 3と 配線基板 2との間に充填される (ステップ S 14)。
[0023] 次に、図 4Dに示すように、チップ保持部 91による ICチップ 3の保持を解除し、押圧 ツール 92を介して ICチップ 3を配線基板 2の上面 21に押圧する。これにより、少なく とも ICチップ 3のバンプ 33の突起部 331と配線基板 2の電極 23が圧接されて接続す る。このとき、配線基板 2は ICチップ 3の押圧力により橈み、配線基板 2のバンプ 33近 傍部分が、例えば下側に変形する。そして、回路基板 2のバンプ 33から少し離れた 周囲の部分は、例えば上側に変形して ICチップ 3の下面 311に近接する。特に、 IC チップ 3のチップ本体 31のエッジ近傍とバンプ 33間の中央近傍（隣接する 2つのバ ンプ 33を結ぶ直線の中央近傍）において、配線基板 2と ICチップ 3とが近接する。
[0024] また、配線基板 2上では、 ICチップ 3の押圧により、異方導電性榭脂 4aはバンプ 33 の周囲へと押し広げられるとともに、接着剤 5aもさらに押し広げられる。なお、ステツ プ SI 1にお 、て、バンプ 33の先端部の突起部 331に付与された異方導電性榭脂 4a の量は少量である。そのため、バンプ 33により押し広げられた異方導電性榭脂 4aは 、 ICチップ 3のチップ本体 31のエッジよりも外側までは広がらず、チップ本体 31と配 線基板 2との間のバンプ 33近傍に留まる。これにより、バンプ 33と電極 23との間では 、バンプ 33と電極 23とが圧接による接続とともに、異方導電性榭脂 4a内の導電性粒 子が押し潰されて電気的に確実に接続される。
[0025] このとき、 ICチップ 3の配線基板 2に対する押圧と同時に、押圧ツール 92に設けら れたヒータ（図示せず）により、 ICチップ 3が配線基板 2に押圧された状態で押圧ツー ル 92を介して加熱される。そして、 ICチップ 3の複数のバンプ 33に付与された異方 導電性榭脂 4aは、熱により硬化する。これにより、図 2に示すように、 ICチップ 3のェ ッジよりも内側において複数のバンプ 33を個別に覆う複数の第 1榭脂層 4が形成され る。
[0026] このように、 ICチップ 3の押圧および加熱により、 ICチップ 3がバンプ 33を挟んで配 線基板 2のアンテナ 22 (図 1参照）の電極 23と電気的〖こ接続されるとともに、 ICチッ プ 3が配線基板 2に接合されて実装される。このとき、接着剤 5aも熱で硬化して、 IC チップ 3と配線基板 2との間の空間を封止する第 2榭脂層 5が形成され、 ICチップ 3が 配線基板 2に強固に固定される (ステップ S15)。上記により、配線基板 2に ICチップ 3が実装され回路基板 1が作製される。
[0027] その後、回路基板 1の両側の主面が、例えばポリカーボネートなどで形成された力 バーシート等により覆われて ICカードが作製される。なお、このとき、 ICカードの厚さ は、例えば約 0. 76mmで形成される。
[0028] 以上で説明したように、本実施の形態の回路基板 1によれば、少なくとも ICチップ 3 のバンプ 33の先端部の突起部 331に異方導電性榭脂 4aを少量だけ付与する。これ により、 ICチップ 3の実装時に異方導電性榭脂 4aに含まれる導電性粒子が、 ICチッ プ 3のチップ本体 31のエッジよりも外側やバンプ 33間の中央近傍へ広がることを防 止できる。すなわち、導電性粒子を、バンプ 33と配線基板 2との接合部および接合部 の近傍のみに選択的に存在させることができる。さらに、本実施の形態の回路基板 1 では、配線基板 2の上面 21と ICチップ 3の下面 311との間の距離が小さくなつている 箇所に導電性粒子が到達することを防止できる。その結果、その箇所における配線 基板 2とチップ本体 31との導通やバンプ 33間の導通を防ぐことにより、 ICチップ 3の 短絡等の実装不良を防止し、接続等の信頼性に優れた回路基板 1を実現できる。
[0029] また、本実施の形態の回路基板 1の製造方法によれば、複数のバンプ 33に付与さ れた異方導電性榭脂 4aにより、 ICチップ 3のエッジよりも内側にぉ 、て複数のバンプ 33を個別に覆う複数の第 1榭脂層 4が形成される。これにより、異方導電性榭脂 4aが ICチップ 3のエッジやバンプ 33間の中央に到達することが防止される。その結果、そ の部位への導電性粒子の到達をより確実に防止し、 ICチップ 3の実装不良の発生を さらに確実に防止できる。そのため、本実施の形態の回路基板 1の製造方法は、例 えば、厚さ 5 m以上 50 m以下の薄く橈みやすい配線基板 2に対する ICチップ 3 等の電子部品の実装に適している。 [0030] また、本実施の形態では、層状の異方導電性榭脂 40に ICチップ 3のバンプ 33を接 触させて、バンプ 33の突起部 331に容易に異方導電性榭脂 4aを付与することがで きるため、回路基板 1の生産性を向上することができる。また、 ICチップ 3のバンプ 33 を先端部に突起部 331を有するスタッドバンプで形成することにより、バンプ 33の先 端部の凹凸により異方導電性榭脂 4aを確実に、かつバンプ 33の封止に必要な量だ け付着させて保持することができる。
[0031] また、本実施の形態では、第 2榭脂層 5で ICチップ 3を配線基板 2に強固に固定す るとともに、チップ本体 31と配線基板 2との間を封止して ICチップ 3の実装不良をより 確実に防止し、回路基板 1の信頼性をより一層向上することができる。
[0032] なお、本実施の形態の回路基板によれば、特に、 ICチップ 3のチップ本体 31に、例 えば絶縁性膜等の形成による導通防止処理を行う必要がないため、それによる IC力 ードの通信特性への影響を防止できる。そのため、アンテナが設けられた配線基板 を用いる ICタグのインレット等の回路基板などに特に適している。
[0033] 以上、本発明の実施の形態について説明してきたが、本発明は上記実施の形態に 限定されるものではなぐ以下に示すような様々な変更が可能である。
[0034] すなわち、上記実施の形態では、層状の異方導電性榭脂 40に ICチップ 3のバンプ 33を接触させて、その先端部の突起部 331に異方導電性榭脂 4aを付与する例で説 明したが、これに限られない。例えば、デイスペンサ等により、各バンプ 33の先端部 に異方導電性榭脂 4aを順次付与してもよ ヽ。
[0035] また、上記実施の形態では、接着剤 5aを、配線基板 2の電極 23以外の一部の領 域に付与する例で説明したが、これに限られない。例えば、接着剤 5aを、配線基板 2 の上面 21上の ICチップ 3が実装される領域のうち、複数のバンプ 33が接合される予 定の複数の領域の周囲を囲むように付与してもよい。このとき、周囲の全周に形成さ れる接着剤 5aの一部に空気抜き用のために付与しな ヽ部分を設けることが好ま 、
[0036] また、上記実施の形態では、 ICカードのインレットを例に説明した力 これに限られ ない。例えば、 ICタグなどのインレットの製造に適用してもよぐ COF (chip on film )法によるディスプレイ等のドライバ ICの実装等に適用してもよい。 [0037] また、上記実施の形態では、配線基板 2に実装される電子部品 3として、記憶素子 などの ICチップ 3を例に説明したが、これに限られない。例えば、チップサイズパッケ ージ（CSP)のようにバンプを有するモールドタイプの ICチップや、受動部品であるチ ップ部品であってもよぐ実装される電子部品は複数であってもよ 、。
[0038] また、上記実施の形態では、配線基板 2として、 PETを例に説明した力 これに限ら れない。例えば、 PEEK (ポリエーテルエーテルケトン)やポリイミド等により形成され た可撓'性の基板であってもよ 、。
産業上の利用可能性
[0039] 本発明は、 ICカードや ICタグのインレット等として用いられる回路基板や他の様々 な回路基板に利用可能である。

Claims

請求の範囲
[1] a)電子部品の複数のバンプのみに導電性粒子を含む異方導電性榭脂を付与するス テツプと、
b)前記異方導電性榭脂を介して可撓性の配線基板の主面上に前記電子部品を配 置するステップと、
c)前記電子部品を前記配線基板に押圧して前記複数のバンプに付与された前記異 方導電性榭脂を硬化させ、前記複数のバンプを前記配線基板の配線に接合するス テツプと、
を含むことを特徴とする回路基板の製造方法。
[2] 前記 c)ステップにおいて、前記異方導電性榭脂を硬化させることにより、前記電子部 品のエッジよりも内側において前記複数のバンプを個別に覆う第 1榭脂層が形成さ れることを特徴とする請求項 1に記載の回路基板の製造方法。
[3] 前記 a)ステップにおける前記異方導電性榭脂の付与が、層状の異方導電性榭脂に 前記電子部品の前記複数のバンプのみを接触させることにより行われることを特徴と する請求項 1に記載の回路基板の製造方法。
[4] 前記 b)ステップよりも前に、前記配線基板上の前記電子部品が実装される予定の領 域のうち、前記複数のバンプが接合される予定の領域以外の一部の領域に非導電 性の接着剤を付与するステップと、
前記 c)ステップと並行して、前記接着剤を硬化させて第 2榭脂層を形成し前記電子 部品を前記配線基板に固定するステップと、
をさらに含むことを特徴とする請求項 1に記載の回路基板の製造方法。
[5] 前記複数のバンプが、先端部に突起部を有するボールバンプであることを特徴とす る請求項 1に記載の回路基板の製造方法。
[6] 前記電子部品が、所定の情報を記憶する記憶素子であり、
前記配線基板が、前記電子部品と電気的に接続されて前記電子部品に記憶されて
V、る前記所定の情報の読み取りに利用される無線通信用のアンテナを備えることを 特徴とする請求項 1に記載の回路基板の製造方法。
[7] 前記配線基板の厚さが、 5 m以上 50 m以下であることを特徴とする請求項 1に記 載の回路基板の製造方法。
[8] 可撓性の配線基板と、
前記配線基板の主面上に複数のバンプを介して実装される電子部品と、 導電性粒子を含む異方導電性榭脂により形成され、前記複数のバンプを個別に覆う 第 1樹脂層と、
前記電子部品と前記配線基板を固定する第 2榭脂層と、
を備えることを特徴とする回路基板。
[9] 前記第 1榭脂層が、前記電子部品のエッジよりも内側に位置することを特徴とする請 求項 8に記載の回路基板。
[10] 前記電子部品が、所定の情報を記憶する記憶素子であり、
前記配線基板が、前記電子部品と電気的に接続されて前記電子部品に記憶されて
V、る前記所定の情報の読み取りに利用される無線通信用のアンテナを備えることを 特徴とする請求項 8に記載の回路基板。
PCT/JP2007/051542 2006-02-13 2007-01-31 回路基板および回路基板の製造方法 WO2007094167A1 (ja)

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