JP2005111928A - 電子回路装置およびその製造方法並びに電子回路装置の製造装置 - Google Patents
電子回路装置およびその製造方法並びに電子回路装置の製造装置 Download PDFInfo
- Publication number
- JP2005111928A JP2005111928A JP2003352019A JP2003352019A JP2005111928A JP 2005111928 A JP2005111928 A JP 2005111928A JP 2003352019 A JP2003352019 A JP 2003352019A JP 2003352019 A JP2003352019 A JP 2003352019A JP 2005111928 A JP2005111928 A JP 2005111928A
- Authority
- JP
- Japan
- Prior art keywords
- cover
- substrate
- electronic component
- circuit device
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/0772—Physical layout of the record carrier
- G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】配線パターン11が形成された基板12と、配線パターン11の端子部11Aに対し突起電極13Aが接触して導通接続された電子部品13と、基板12に対向する位置に配置され、電子部品13を上記基板12とで挟むカバー14と、突起電極13Aと端子部11Aとの導通接続部を除く接続領域の空間部を含めて上記基板12と上記カバー14との間に充填された熱可塑性樹脂からなる樹脂層15とからなり、樹脂層15により、電子部品13と基板12および基板12とカバー14とがそれぞれ接着された構成とする。
【選択図】図1
Description
図1は、本発明の第1の実施の形態にかかる電子回路装置としてのIC−TAG10の要部断面図である。また、図2はこのIC−TAG10の基板上面からみた平面図である。なお、図2においては、カバーおよび樹脂層等は図面の簡単化のために図示していない。
図9は、本発明の第2の実施の形態による電子回路装置の要部断面図である。本実施の形態においても、電子回路装置としてIC−TAG70を例として説明するので、図1から図8までの要素と同じ要素については同じ符号を付している。
1A 接合部材
2,12,18 基板
3 IC
3A,13A,20A 突起電極
4 スぺーサ
4A 開口部
5,14,47 カバー
5A,21,32 熱可塑性樹脂層
6,15,15A,150 樹脂層
7 ICカード
10,50,70,80 IC−TAG
11A,17A 端子部
12A 基板シート
13 IC(電子部品)
14A カバー用シート
16 補強板
19 外部接続端子
19A 導通部
20 電子部品
22 樹脂シート
22A 搬送用シート
23 加熱・加圧ローラ
24,37,42 冷却部
25 樹脂層付き基板シート
26,27 リール
28 加熱機
29 ヒータ付き搬送台
30 マウント機
31 チップ付き基板シート
33,44 カバー用樹脂シート
36,39 加圧ローラ
36A,36B,36C,38,39A,39B,39C,40 ローラ
41 加熱部
60 電子回路装置
Claims (22)
- 配線パターンが形成された基板と、
前記配線パターンの端子部に対し突起電極が接触して導通接続された電子部品と、
前記基板に対向する位置に配置され、前記電子部品を前記基板とで挟むカバーと、
前記突起電極と前記端子部との導通接続部を除く接続領域の空間部を含めて前記基板と前記カバーとの間に充填された熱可塑性樹脂からなる樹脂層とからなり、
前記樹脂層により、前記電子部品と前記基板および前記基板と前記カバーとがそれぞれ接着された構成からなることを特徴とする電子回路装置。 - 前記電子部品の前記カバーに対向する面と前記カバーとが前記樹脂層により接着固定された構成からなることを特徴とする請求項1に記載の電子回路装置。
- 前記電子部品の前記カバーに対向する面と前記カバーとが密接する構成からなることを特徴とする請求項1に記載の電子回路装置。
- 前記電子部品の前記カバーに対向する面と前記カバー間には、さらに補強板が配設されている構成からなることを特徴とする請求項2または請求項3に記載の電子回路装置。
- 前記補強板は、前記カバーに対して接着固定された構成からなることを特徴とする請求項4に記載の電子回路装置。
- 前記補強板は、前記電子部品に対して接着固定された構成からなることを特徴とする請求項4または請求項5に記載の電子回路装置。
- 前記電子部品の前記突起電極と前記配線パターンの前記端子部との前記導通接続部は、前記突起電極と前記端子部の少なくとも一方が変形して他方に沿った曲面構成からなることを特徴とする請求項1から請求項6までのいずれかに記載の電子回路装置。
- 前記導通接続部は、前記突起電極の先端部が前記端子部を突き抜けて前記基板表面まで到達した構成からなることを特徴とする請求項7に記載の電子回路装置。
- 前記電子部品は、一方の表面に前記突起電極が形成された半導体集積回路素子であり、前記基板上に1個以上が接着された構成からなることを特徴とする請求項1から請求項8までのいずれかに記載の電子回路装置。
- 前記基板には少なくともアンテナを構成する前記配線パターンが形成されており、前記配線パターンの前記端子部と前記半導体集積回路素子の前記突起電極とが導通接続されて、非接触で外部機器と情報を送受する機能を有することを特徴とする請求項9に記載の電子回路装置。
- 前記基板には、前記電子部品を接着する面とは反対側の面に外部機器と接続するための外部接続端子が形成され、かつ前記外部接続端子と前記配線パターンとは導通接続されており、前記配線パターンの前記端子部と前記半導体集積回路素子の前記突起電極とが導通接続されていて、前記外部接続端子により前記外部機器と情報を送受する機能を有することを特徴とする請求項9に記載の電子回路装置。
- 配線パターンが形成された基板の表面に熱可塑性樹脂からなる樹脂層を形成する工程と、
突起電極を有する電子部品を前記配線パターンの端子部と位置合せし、前記樹脂層に仮固定する工程と、
仮固定された前記電子部品上にカバーを配置し、前記樹脂層を加熱して軟化させながら前記カバーを介して前記電子部品を押圧し、前記配線パターンの前記端子部と前記突起電極間の前記樹脂層を流動させ排除して、前記端子部と前記突起電極とを接触させて導通接続する押圧工程と、
前記樹脂層を冷却して、前記電子部品と前記基板および前記基板と前記カバーとをそれぞれ接着固定し、前記突起電極と前記端子部との導通接続を保持する接着固定工程とを具備することを特徴とする電子回路装置の製造方法。 - 前記仮固定工程において、前記突起電極と前記端子部とを位置合せした後、前記突起電極または前記電子部品の本体の一部を前記樹脂層中に埋め込み仮固定することを特徴とする請求項12に記載の電子回路装置の製造方法。
- 前記仮固定工程において、前記樹脂層を加熱し軟化させて、前記突起電極または前記電子部品の本体の一部を前記樹脂層中に埋め込み仮固定することを特徴とする請求項12に記載の電子回路装置の製造方法。
- 前記カバーには、前記電子部品に対向する面上に前記熱可塑性樹脂と同じ材料からなる熱可塑性樹脂層が形成されており、
前記押圧工程では、前記熱可塑性樹脂層が形成された前記カバーを介して前記電子部品を押圧して前記突起電極と前記端子部との導通接続を行い、
前記接着固定工程では、前記カバーと前記基板とに形成された前記熱可塑性樹脂により、前記電子部品が前記基板および前記カバーの両方と接着固定されることを特徴とする請求項12から請求項14までのいずれかに記載の電子回路装置の製造方法。 - 前記カバーには前記電子部品と対向する位置に補強板が保持されており、
前記押圧工程では、前記補強板が配置された前記カバーを介して前記電子部品を押圧して前記突起電極と前記端子部との導通接続を行い、
前記接着固定工程では、前記電子部品が前記補強板に密接した状態で、前記基板および前記カバーと接着固定されることを特徴とする請求項12から請求項14までのいずれかに記載の電子回路装置の製造方法。 - 前記カバーには前記電子部品と対向する位置に補強板が保持され、かつ前記補強板を含めた前記カバー面上に前記熱可塑性樹脂と同じ材料からなる熱可塑性樹脂層が形成されており、
前記押圧工程では、前記補強板および前記熱可塑性樹脂層が形成された前記カバーを介して前記電子部品を押圧して前記突起電極と前記端子部との導通接続を行い、
前記接着固定工程では、前記カバーと前記基板とに形成された前記熱可塑性樹脂により、前記電子部品が前記補強板および前記基板と接着固定されることを特徴とする記載の請求項12から請求項14までのいずれかに電子回路装置の製造方法。 - 前記カバーが可撓性を有する材料からなり、
前記押圧工程は、両側に対向して設けられた一対のローラを配置した押圧手段を用いて、前記電子部品が挟持された前記基板と前記カバーとを前記ローラ間を通過させて行うことを特徴とする請求項12から請求項17までのいずれかに記載の電子回路装置の製造方法。 - 前記押圧手段は、押圧力またはローラ間隔の異なる両側に対向して設けられた一対の前記ローラを複数組有し、前記電子部品が挟持された前記基板と前記カバーとが複数組の前記ローラを通過する順番に押圧力を増大、またはローラ間隔を狭くした構成であり、
前記押圧工程は前記電子部品が挟持された前記基板と前記カバーを複数組の前記ローラを通過させて行うことを特徴とする請求項18に記載の電子回路装置の製造方法。 - 配線パターンが形成された基板表面に熱可塑性樹脂からなる樹脂層を形成する樹脂層形成手段と、
突起電極を有する電子部品を前記配線パターンの端子部と位置合せし、前記樹脂層により仮固定する手段と、
仮固定された前記電子部品上にカバーを配置し、前記熱可塑性樹脂を加熱して軟化させながら前記カバーを介して前記電子部品を押圧し、前記配線パターンの前記端子部と前記突起電極間の前記熱可塑性樹脂を流動させ排除して、前記端子部と前記突起電極とを接触させて導通接続する押圧手段と、
前記樹脂層を冷却して、前記電子部品と前記基板および前記基板と前記カバーとをそれぞれ接着固定し、前記突起電極と前記端子部との導通接続を保持する接着固定手段とを具備することを特徴とする電子回路装置の製造装置。 - 前記押圧手段と前記接着固定手段とは、両側に対向して設けられた一対のローラを複数組配置した構成からなり、前記電子部品が挟持された前記基板と前記カバーとを前記ローラ間を通過させることで、連続的に押圧工程と接着固定工程とが行われることを特徴とする請求項20に記載の電子回路装置の製造装置。
- 複数組の前記ローラには、前記電子部品が挟持された前記基板と前記カバーとの入口側に加熱手段が設けられ、出口側に冷却手段が設けられた構成からなることを特徴とする請求項21に記載の電子回路装置の製造装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003352019A JP4479209B2 (ja) | 2003-10-10 | 2003-10-10 | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 |
US10/959,324 US20050093172A1 (en) | 2003-10-10 | 2004-10-07 | Electronic circuit device, and method and apparatus for manufacturing the same |
CNB2004100808344A CN100365784C (zh) | 2003-10-10 | 2004-10-09 | 电子电路装置及其制造方法以及制造装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003352019A JP4479209B2 (ja) | 2003-10-10 | 2003-10-10 | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005111928A true JP2005111928A (ja) | 2005-04-28 |
JP4479209B2 JP4479209B2 (ja) | 2010-06-09 |
Family
ID=34543084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003352019A Expired - Fee Related JP4479209B2 (ja) | 2003-10-10 | 2003-10-10 | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20050093172A1 (ja) |
JP (1) | JP4479209B2 (ja) |
CN (1) | CN100365784C (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007094167A1 (ja) * | 2006-02-13 | 2007-08-23 | Matsushita Electric Industrial Co., Ltd. | 回路基板および回路基板の製造方法 |
JP2009514703A (ja) * | 2005-11-02 | 2009-04-09 | チエツクポイント システムズ, インコーポレーテツド | インモールドのチップ取り付け |
JP2009521768A (ja) * | 2005-12-30 | 2009-06-04 | インテル コーポレイション | チップスペーサ集積rfidタグ、製造方法及びシステム |
JPWO2007083352A1 (ja) * | 2006-01-17 | 2009-06-11 | スパンション エルエルシー | 半導体装置およびその製造方法 |
JPWO2014006787A1 (ja) * | 2012-07-04 | 2016-06-02 | パナソニックIpマネジメント株式会社 | 電子部品実装構造体、icカード、cofパッケージ |
WO2016084703A1 (ja) * | 2014-11-25 | 2016-06-02 | 旭硝子株式会社 | 基板の貼合装置及び貼合方法並びに電子デバイスの製造方法 |
JP2021039976A (ja) * | 2019-08-30 | 2021-03-11 | 日亜化学工業株式会社 | 発光モジュール及びその製造方法 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8119458B2 (en) * | 2005-02-01 | 2012-02-21 | Nagraid S.A. | Placement method of an electronic module on a substrate |
US7785932B2 (en) * | 2005-02-01 | 2010-08-31 | Nagraid S.A. | Placement method of an electronic module on a substrate and device produced by said method |
US8067253B2 (en) * | 2005-12-21 | 2011-11-29 | Avery Dennison Corporation | Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film |
NL1030865C2 (nl) * | 2006-01-06 | 2007-07-09 | Sdu Identification Bv | Identiteitsdocument met chip. |
EP1887497B1 (en) * | 2006-08-10 | 2015-05-27 | Fujitsu Limited | RFID tag |
DE102006044525B3 (de) * | 2006-09-21 | 2008-01-31 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung von gemeinsam bereitstellbaren flexiblen integrierten Schaltkreisen |
WO2008061554A1 (de) * | 2006-11-24 | 2008-05-29 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Elektronische, insbesondere mikroelektronische funktionsgruppe und verfahren zu deren herstellung |
JP2008171331A (ja) * | 2007-01-15 | 2008-07-24 | Brother Ind Ltd | タグテープ、タグテープロール、無線タグラベル |
JP5145881B2 (ja) * | 2007-11-07 | 2013-02-20 | 富士通株式会社 | Rfidタグ |
JP4753960B2 (ja) * | 2008-03-31 | 2011-08-24 | 三洋電機株式会社 | 半導体モジュール、半導体モジュールの製造方法 |
US8695207B2 (en) * | 2008-06-02 | 2014-04-15 | Nxp B.V. | Method for manufacturing an electronic device |
US20110073357A1 (en) * | 2008-06-02 | 2011-03-31 | Nxp B.V. | Electronic device and method of manufacturing an electronic device |
JP5199010B2 (ja) * | 2008-10-01 | 2013-05-15 | 富士通株式会社 | Rfidタグの製造方法およびrfidタグ |
FR2937165B1 (fr) * | 2008-10-15 | 2011-04-08 | Fasver | Procede de connexion d'un microcircuit a des bornes d'une antenne imprimee sur un support |
FR2951866B1 (fr) * | 2009-10-27 | 2011-11-25 | Arjowiggins Security | Procede de fabrication d'un support integrant un dispositif electronique |
DE102010064453B4 (de) | 2010-10-18 | 2017-12-21 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Herstellen eines Chip-Package |
DE102010042567B3 (de) | 2010-10-18 | 2012-03-29 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Herstellen eines Chip-Package und Chip-Package |
EP2461275A1 (en) * | 2010-12-02 | 2012-06-06 | Gemalto SA | Security Document and method of manufacturing security document |
DE102012025433B4 (de) * | 2012-12-21 | 2015-10-01 | Karlsruher Institut für Technologie | Verfahren zur Gehäusung von Sub-Millimeterwellen-Halbleiterschaltungen sowie mit dem Verfahren herstellbares Halbleitermodul |
FR3000822A1 (fr) * | 2013-01-08 | 2014-07-11 | Ask Sa | Dispositif radiofrequence en plastique pour carte a puce sans contact ou document de securite ou de valeur sans contact et son procede de fabrication pour eviter les fissures |
JP2015172683A (ja) * | 2014-03-12 | 2015-10-01 | 富士通オプティカルコンポーネンツ株式会社 | 光モジュール |
JP6679378B2 (ja) * | 2016-03-30 | 2020-04-15 | 東レエンジニアリング株式会社 | 実装装置および実装方法 |
US10636745B2 (en) | 2017-09-27 | 2020-04-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
EP3633716A1 (en) | 2018-10-05 | 2020-04-08 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Package with embedded electronic component being encapsulated in a pressureless way |
CN113228833A (zh) * | 2018-12-31 | 2021-08-06 | 3M创新有限公司 | 软基板上的柔性电路 |
FR3123778A1 (fr) * | 2021-06-07 | 2022-12-09 | Eyco | Procédé de fabrication d’un circuit imprimé intégrant un composant électronique et module de carte à puce obtenu par ledit procédé. |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5528222A (en) * | 1994-09-09 | 1996-06-18 | International Business Machines Corporation | Radio frequency circuit and memory in thin flexible package |
DE19527359A1 (de) * | 1995-07-26 | 1997-02-13 | Giesecke & Devrient Gmbh | Schaltungseinheit und Verfahren zur Herstellung einer Schaltungseinheit |
US5874780A (en) * | 1995-07-27 | 1999-02-23 | Nec Corporation | Method of mounting a semiconductor device to a substrate and a mounted structure |
DE59611233D1 (de) * | 1995-08-01 | 2005-07-14 | Austria Card | Datenträger mit einem einen bauteil aufweisenden modul und mit einer spule und verfahren zum herstellen eines solchen datenträgers |
US5892661A (en) * | 1996-10-31 | 1999-04-06 | Motorola, Inc. | Smartcard and method of making |
JP2924830B2 (ja) * | 1996-11-15 | 1999-07-26 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5837153A (en) * | 1997-01-15 | 1998-11-17 | Kawan; Joseph C. | Method and system for creating and using a logotype contact module with a smart card |
JPH10270496A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法 |
FR2775810B1 (fr) * | 1998-03-09 | 2000-04-28 | Gemplus Card Int | Procede de fabrication de cartes sans contact |
FR2778308B1 (fr) * | 1998-04-30 | 2006-05-26 | Schlumberger Systems & Service | Procede de realisation d'un composant electronique et composant electronique |
SG80077A1 (en) * | 1998-10-19 | 2001-04-17 | Sony Corp | Semiconductor integrated circuit card manufacturing method, and semiconductor integrated circuit card |
FR2790849B1 (fr) * | 1999-03-12 | 2001-04-27 | Gemplus Card Int | Procede de fabrication pour dispositif electronique du type carte sans contact |
JP3517374B2 (ja) * | 1999-05-21 | 2004-04-12 | 新光電気工業株式会社 | 非接触型icカードの製造方法 |
JP2001188891A (ja) * | 2000-01-05 | 2001-07-10 | Shinko Electric Ind Co Ltd | 非接触型icカード |
JP2001217380A (ja) * | 2000-02-04 | 2001-08-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP3813797B2 (ja) * | 2000-07-07 | 2006-08-23 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP3945968B2 (ja) * | 2000-09-06 | 2007-07-18 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
JP2002151551A (ja) * | 2000-11-10 | 2002-05-24 | Hitachi Ltd | フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
FR2836242B1 (fr) * | 2002-02-18 | 2004-04-30 | Synelec Telecom Multimedia | Procede de fabrication d'un ecran de retroprojection |
US7138583B2 (en) * | 2002-05-08 | 2006-11-21 | Sandisk Corporation | Method and apparatus for maintaining a separation between contacts |
-
2003
- 2003-10-10 JP JP2003352019A patent/JP4479209B2/ja not_active Expired - Fee Related
-
2004
- 2004-10-07 US US10/959,324 patent/US20050093172A1/en not_active Abandoned
- 2004-10-09 CN CNB2004100808344A patent/CN100365784C/zh not_active Expired - Fee Related
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009514703A (ja) * | 2005-11-02 | 2009-04-09 | チエツクポイント システムズ, インコーポレーテツド | インモールドのチップ取り付け |
JP4762317B2 (ja) * | 2005-11-02 | 2011-08-31 | チエツクポイント システムズ, インコーポレーテツド | インモールドのチップ取り付け |
JP2009521768A (ja) * | 2005-12-30 | 2009-06-04 | インテル コーポレイション | チップスペーサ集積rfidタグ、製造方法及びシステム |
US8317107B2 (en) | 2005-12-30 | 2012-11-27 | Intel Corporation | Chip-spacer integrated radio frequency ID tags, methods of making same, and systems containing same |
JP5036563B2 (ja) * | 2006-01-17 | 2012-09-26 | スパンション エルエルシー | 半導体装置およびその製造方法 |
JPWO2007083352A1 (ja) * | 2006-01-17 | 2009-06-11 | スパンション エルエルシー | 半導体装置およびその製造方法 |
US8772953B2 (en) | 2006-01-17 | 2014-07-08 | Spansion Llc | Semiconductor device and programming method |
US8291582B2 (en) | 2006-02-13 | 2012-10-23 | Panasonic Corporation | Circuit board and process for producing the same |
WO2007094167A1 (ja) * | 2006-02-13 | 2007-08-23 | Matsushita Electric Industrial Co., Ltd. | 回路基板および回路基板の製造方法 |
JP5029597B2 (ja) * | 2006-02-13 | 2012-09-19 | パナソニック株式会社 | カード型記録媒体およびカード型記録媒体の製造方法 |
JPWO2007094167A1 (ja) * | 2006-02-13 | 2009-07-02 | パナソニック株式会社 | 回路基板および回路基板の製造方法 |
US8866021B2 (en) | 2006-02-13 | 2014-10-21 | Panasonic Corporation | Circuit board and process for producing the same |
JPWO2014006787A1 (ja) * | 2012-07-04 | 2016-06-02 | パナソニックIpマネジメント株式会社 | 電子部品実装構造体、icカード、cofパッケージ |
WO2016084703A1 (ja) * | 2014-11-25 | 2016-06-02 | 旭硝子株式会社 | 基板の貼合装置及び貼合方法並びに電子デバイスの製造方法 |
JP2021039976A (ja) * | 2019-08-30 | 2021-03-11 | 日亜化学工業株式会社 | 発光モジュール及びその製造方法 |
US11316081B2 (en) | 2019-08-30 | 2022-04-26 | Nichia Corporation | Light-emitting module and method for manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
JP4479209B2 (ja) | 2010-06-09 |
CN100365784C (zh) | 2008-01-30 |
US20050093172A1 (en) | 2005-05-05 |
CN1606142A (zh) | 2005-04-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4479209B2 (ja) | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 | |
JP4737505B2 (ja) | Icタグインレット及びicタグインレットの製造方法 | |
KR100419466B1 (ko) | 전자파 판독 가능한 데이터 캐리어, 배선기판 및 그들의제조방법 | |
FI112121B (fi) | Älytarraraina, menetelmä sen valmistamiseksi, menetelmä kantorainan valmistamiseksi ja älytarrarainan älytarran rakenneosa | |
KR100634239B1 (ko) | 보강판 부착 장치 및 부착 방법 | |
KR100536978B1 (ko) | 전자 부품 모듈의 제조 방법 및 전자파 판독 가능한데이터 캐리어의 제조 방법 | |
US7776654B2 (en) | Method of producing electronic apparatus | |
JP4518024B2 (ja) | 電子装置 | |
US8273605B2 (en) | Manufacturing method for electronic device having IC chip and antenna electrically connected by bridging plate | |
JP4860494B2 (ja) | 電子装置の製造方法 | |
JP2006196526A (ja) | 半導体チップの実装方法、配線回路基板の構造、及び配線回路基板の製造方法 | |
KR20090128370A (ko) | 프린트 기판 조립체 및 전자 장치 | |
JP4386038B2 (ja) | 電子装置の製造方法 | |
JP3509573B2 (ja) | フレキシブル基板用テープ材、フレキシブル基板の製造方法、半導体装置の製造方法及び液晶装置の製造方法 | |
MX2008012339A (es) | Metodos para sujetar un montaje de circuito integrado de un chip invertido a un sustrato. | |
JP3584404B2 (ja) | 半導体チップの実装方法 | |
JPH1159036A (ja) | 非接触icカード及びその製造方法 | |
TWI336223B (en) | Electronic device and method of manufacturing same | |
US8299925B2 (en) | RFID tag and manufacturing method thereof | |
JP2002312749A (ja) | コンビ型icカードの製造方法 | |
JP5303997B2 (ja) | ワイヤアンテナを用いたrfidタグインレットの製造方法 | |
JP4529216B2 (ja) | Icカード及びその製造方法 | |
JP2003091709A (ja) | Icカード及びその製造方法 | |
JPH09283570A (ja) | フィルムキャリア | |
TW201316865A (zh) | 熱壓接合雷射蝕刻銅墊至板上連接式晶片模組之方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060314 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20060412 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081209 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090206 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090303 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090408 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091119 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100223 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100308 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130326 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130326 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140326 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |