JP3260583B2 - ダイナミック型半導体メモリおよびそのテスト方法 - Google Patents

ダイナミック型半導体メモリおよびそのテスト方法

Info

Publication number
JP3260583B2
JP3260583B2 JP07882695A JP7882695A JP3260583B2 JP 3260583 B2 JP3260583 B2 JP 3260583B2 JP 07882695 A JP07882695 A JP 07882695A JP 7882695 A JP7882695 A JP 7882695A JP 3260583 B2 JP3260583 B2 JP 3260583B2
Authority
JP
Japan
Prior art keywords
sense amplifier
signal
circuit
test
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07882695A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08279287A (ja
Inventor
禎彦 広瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP07882695A priority Critical patent/JP3260583B2/ja
Priority to US08/627,126 priority patent/US5625597A/en
Priority to KR1019960009958A priority patent/KR100203529B1/ko
Priority to TW085104378A priority patent/TW302520B/zh
Publication of JPH08279287A publication Critical patent/JPH08279287A/ja
Application granted granted Critical
Publication of JP3260583B2 publication Critical patent/JP3260583B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
JP07882695A 1995-04-04 1995-04-04 ダイナミック型半導体メモリおよびそのテスト方法 Expired - Fee Related JP3260583B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP07882695A JP3260583B2 (ja) 1995-04-04 1995-04-04 ダイナミック型半導体メモリおよびそのテスト方法
US08/627,126 US5625597A (en) 1995-04-04 1996-04-03 DRAM having test circuit capable of performing function test of refresh counter and measurement of refresh cycle simultaneously
KR1019960009958A KR100203529B1 (ko) 1995-04-04 1996-04-03 다이나믹형 반도체메모리 및 그 테스트방법
TW085104378A TW302520B (enExample) 1995-04-04 1996-04-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07882695A JP3260583B2 (ja) 1995-04-04 1995-04-04 ダイナミック型半導体メモリおよびそのテスト方法

Publications (2)

Publication Number Publication Date
JPH08279287A JPH08279287A (ja) 1996-10-22
JP3260583B2 true JP3260583B2 (ja) 2002-02-25

Family

ID=13672645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07882695A Expired - Fee Related JP3260583B2 (ja) 1995-04-04 1995-04-04 ダイナミック型半導体メモリおよびそのテスト方法

Country Status (4)

Country Link
US (1) US5625597A (enExample)
JP (1) JP3260583B2 (enExample)
KR (1) KR100203529B1 (enExample)
TW (1) TW302520B (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3544073B2 (ja) * 1996-09-03 2004-07-21 株式会社 沖マイクロデザイン 半導体メモリ装置のテスト方法および半導体メモリ装置
US5754557A (en) * 1996-10-10 1998-05-19 Hewlett-Packard Co. Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller
US5877993A (en) * 1997-05-13 1999-03-02 Micron Technology, Inc. Memory circuit voltage regulator
US6173425B1 (en) 1998-04-15 2001-01-09 Integrated Device Technology, Inc. Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams
US6167544A (en) * 1998-08-19 2000-12-26 Stmicroelectronics, Inc. Method and apparatus for testing dynamic random access memory
US6317852B1 (en) * 1998-10-23 2001-11-13 Vanguard International Semiconductor Corporation Method to test auto-refresh and self refresh circuitry
KR100513797B1 (ko) * 1998-12-30 2006-05-11 주식회사 하이닉스반도체 정상동작과 동일한 데이터 패스를 가지는 반도체 소자의 압축테스트 회로
KR100364128B1 (ko) * 1999-04-08 2002-12-11 주식회사 하이닉스반도체 셀프리프레쉬 발진주기 측정장치
KR100548541B1 (ko) * 1999-06-30 2006-02-02 주식회사 하이닉스반도체 반도체 소자의 리프레쉬 특성을 측정하기 위한 테스트 장치 및방법
JP2001167598A (ja) * 1999-12-03 2001-06-22 Mitsubishi Electric Corp 半導体装置
JP2001195897A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体記憶装置
DE10004958A1 (de) * 2000-02-04 2001-08-09 Infineon Technologies Ag Verfahren zum Testen der Refresheinrichtung eines Informationsspeichers
US6246619B1 (en) 2000-02-07 2001-06-12 Vanguard International Semiconductor Corp. Self-refresh test time reduction scheme
US7147657B2 (en) * 2003-10-23 2006-12-12 Aptus Endosystems, Inc. Prosthesis delivery systems and methods
KR100442966B1 (ko) * 2001-12-28 2004-08-04 주식회사 하이닉스반도체 로오 어드레스 카운터의 동작 모니터링 장치
JP3838932B2 (ja) * 2002-03-28 2006-10-25 Ｎｅｃエレクトロニクス株式会社 メモリ装置及びメモリ装置の試験方法
JP2003338177A (ja) 2002-05-22 2003-11-28 Mitsubishi Electric Corp 半導体記憶装置
DE10228527B3 (de) * 2002-06-26 2004-03-04 Infineon Technologies Ag Verfahren zum Überprüfen der Refresh-Funktion eines Informationsspeichers
WO2005024834A2 (en) * 2003-09-05 2005-03-17 Zmos Technology, Inc. Low voltage operation dram control circuits
KR100527553B1 (ko) * 2004-03-11 2005-11-09 주식회사 하이닉스반도체 라이트-검증-리드 기능을 구현하는 ｐｓｒａｍ
TW200721163A (en) * 2005-09-23 2007-06-01 Zmos Technology Inc Low power memory control circuits and methods
DE102006019507B4 (de) * 2006-04-26 2008-02-28 Infineon Technologies Ag Integrierter Halbleiterspeicher mit Testfunktion und Verfahren zum Testen eines integrierten Halbleiterspeichers
JP4899751B2 (ja) * 2006-09-27 2012-03-21 富士通セミコンダクター株式会社 半導体メモリおよび半導体メモリの試験方法
US7986577B2 (en) * 2007-03-19 2011-07-26 Hynix Semiconductor Inc. Precharge voltage supplying circuit
KR100856060B1 (ko) * 2007-04-06 2008-09-02 주식회사 하이닉스반도체 반도체메모리소자의 내부리프레쉬신호 생성장치
JP2011034632A (ja) * 2009-07-31 2011-02-17 Elpida Memory Inc 半導体記憶装置及びそのテスト方法
KR101752154B1 (ko) 2010-11-02 2017-06-30 삼성전자주식회사 로우 어드레스 제어 회로, 이를 포함하는 반도체 메모리 장치 및 로우 어드레스 제어 방법
KR102020553B1 (ko) * 2013-01-17 2019-09-10 삼성전자주식회사 반도체 메모리 장치의 센스앰프 소스 노드 제어회로 및 그에 따른 센스앰프 소스 노드 제어방법
JP6383637B2 (ja) * 2014-10-27 2018-08-29 ルネサスエレクトロニクス株式会社 半導体装置
KR20170013488A (ko) * 2015-07-27 2017-02-07 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US20170148503A1 (en) * 2015-11-23 2017-05-25 Nanya Technology Corporation Dynamic random access memory circuit and voltage controlling method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4347589A (en) * 1979-05-15 1982-08-31 Mostek Corporation Refresh counter test
DE3789987T2 (de) * 1986-03-24 1994-12-15 Nippon Electric Co Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb.
US5321661A (en) * 1991-11-20 1994-06-14 Oki Electric Industry Co., Ltd. Self-refreshing memory with on-chip timer test circuit
JP3001342B2 (ja) * 1993-02-10 2000-01-24 日本電気株式会社 記憶装置
JP3244340B2 (ja) * 1993-05-24 2002-01-07 三菱電機株式会社 同期型半導体記憶装置
JP3059024B2 (ja) * 1993-06-15 2000-07-04 沖電気工業株式会社 半導体記憶回路
US5450364A (en) * 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices

Also Published As

Publication number Publication date
US5625597A (en) 1997-04-29
KR960038981A (ko) 1996-11-21
KR100203529B1 (ko) 1999-06-15
TW302520B (enExample) 1997-04-11
JPH08279287A (ja) 1996-10-22

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