JP2599748Y2 - リード露出型半導体パッケージ - Google Patents

リード露出型半導体パッケージ

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Publication number
JP2599748Y2
JP2599748Y2 JP1993045198U JP4519893U JP2599748Y2 JP 2599748 Y2 JP2599748 Y2 JP 2599748Y2 JP 1993045198 U JP1993045198 U JP 1993045198U JP 4519893 U JP4519893 U JP 4519893U JP 2599748 Y2 JP2599748 Y2 JP 2599748Y2
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JP
Japan
Prior art keywords
lead
chip
semiconductor package
leads
exposed
Prior art date
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Expired - Lifetime
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JP1993045198U
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English (en)
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JPH0629147U (ja
Inventor
基本 車
Original Assignee
エル・ジー・セミコン・カンパニー・リミテッド
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Publication of JP2599748Y2 publication Critical patent/JP2599748Y2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【考案の詳細な説明】
【０００１】
【産業上の利用分野】本考案は、半導体パッケージに関
するものであり、特に、外部連結リードを半導体パッケ
ージ本体の両外方側に突出せずに、パッケージ本体の下
面に露出させて、パッケージの基板占有面積を減少し、
製造工程を簡素化し得るようにした、リード露出型半導
体パッケージに関するものである。
【０００２】
【従来の技術】従来、半導体パッケージにおいては、図
４および図５に示したように、パドル２上面に半導体チ
ップ１が接着剤７により接着され、該半導体チップ１上
面と複数個のインナーリード３とがそれぞれ金属ワイヤ
５によりワイヤボンディングされ、それらインナーリー
ド３にそれぞれアウトリード４が連結されてリードフレ
ームが形成され、それら半導体チップ１、金属ワイヤ５
およびアウトリード４との一部がモールド樹脂６により
成型された後、該成型されたパッケージ本体外方側に突
出されるリードフレームのアウトリード４がそれぞれ適
宜な形態にフォーミングされて、スモールアウトライン
Ｊ−リード型半導体パッケージまたはスモールアウトラ
イン型半導体パッケージ等の多様な形態の半導体パッケ
ージが構成されていた。
【０００３】かつ、前記リードフレームにおいては、図
６に示したように、両方側にそれぞれサイドレール８，
８′が形成され、それらサイドレール８，８′内方側中
央部位に前記パドル２が形成され、該パドル２両方側と
それらサイドレール８，８′間にそれぞれ連結バー９，
９′が連続形成され、それら連結バー９，９′両方側に
前記複数個のインナーリード３およびアウトリード４が
それぞれ形成され、それらインナーリード３およびアウ
トリード４がダンパ１０により前記両方側サイドレール
８，８′にそれぞれ連結されていた。
【０００４】また、このような従来の半導体パッケージ
の製造工程においては、まず、前記半導体チップ１がダ
イシング工程によりそれぞれ１個ずつ切断分離され、そ
れら分離された半導体チップ１は前記パドル２上にそれ
ぞれ前記接着剤７により接着されて硬化され、それら半
導体チップ１と前記複数個のインナーリード３とがそれ
ぞれ金属ワイヤ５により電気的に接続された後、それら
半導体チップ１、各インナーリード３および各金属ワイ
ヤ５とを包含した所定容積部位がモールド樹脂６により
成型されていた。
【０００５】次いで、前記各アウトリード４にそれぞれ
錫または鉛めっきが施され、前記ダンパ１０および各連
結バー９，９′がそれぞれトリミングにより切断除去さ
れた後、それぞれ適宜にフォーミング工程が施されて、
前記のスモールアウトラインＪ−リードパッケージ（Ｓ
ｍａｌｌ Ｏｕｔ Ｌｉｎｅ Ｊ−Ｌｅａｄ Ｐａｃｋ
ａｇｅ）またはスモールアウトラインパッケージ（ＳＯ
Ｐ）、もしくはデュアルインラインパッケージ（Ｄｕａ
ｌ Ｉｎ Ｌｉｎｅ Ｐａｃｋａｇｅ）等の半導体パッ
ケージが製造されていた。
【０００６】
【考案が解決しようとする課題】しかしながら、このよ
うな従来の半導体パッケージにおいては、成型された半
導体パッケージの外方側にアウトリードが突成され、そ
れらアウトリードが所定形状にフォーミングされている
ため、それら半導体パッケージを基板に装着する場合、
それら半導体パッケージの占める面積が大きくなって、
半導体パッケージを基板上に実質的に装着する実装率が
低下するという不都合な点があった。かつ、成型された
半導体パッケージ本体外方側にアウトリードが突成され
ているため、該アウトリードのトリムおよびフォーミン
グ作業時または基板上の装着時に、該アウドリードには
外力により撓みが生じてモールド樹脂の成型部位と突成
されたアウトリード間に界面分離現象が発生し、場合に
よってはその接触部位が破壊されるという不都合な点が
あった。
【０００７】また、半導体パッケージの製造工程が複雑
であるため、製造原価が上昇するという不都合な点があ
った。さらに、製品の電気的特性試験の場合、リード接
触不良品が多く発生し、製品の信頼性が低下するという
不都合な点があった。
【０００８】本考案の目的は、上述の問題点を解決し、
半導体パッケージの基板占有面積をできるだけ減らし、
リードの接触不良品発生と、リードとモールド樹脂間の
破壊現象とを除去し得る、リード露出型半導体パッケー
ジを提供することにある。
【０００９】また、本考案の他の目的は、半導体パッケ
ージの製造工程を簡素化し、製造原価および設備の投資
費を節減し得るようにした、リード露出型半導体パッケ
ージを提供することにある。
【００１０】
【課題を解決するための手段】この発明によるリード露
出型半導体パッケージは、基板連結リードとチップ接続
リードとから構成され、それら基板連結リードとチップ
接続リードとは互いに一体型に延長されて形成され、基
板連結リードがチップ接続リードより下方に位置するよ
うにダウンセットされてあるリードと、リードの基板連
結リードの上面に接着剤を介して付着された半導体チッ
プと、半導体チップの上面とチップ接続リードとを連結
する金属ワイヤと、半導体チップ、金属ワイヤ、チップ
接続リードの全体および基板連結リードの上面を覆うモ
ールド樹脂と、を備え、基板連結リードの下面がモール
ド樹脂の下面側に露出されてあり、 複数個のリードの上
面に半導体チップを載置させてパッケージしたことを特
徴としている。
【００１１】好ましくは、チップ接続リードの一側端に
Ｖ字型切断溝が穿孔形成されているとよい。
【００１２】また、好ましくは、接着剤は、絶縁性両面
テープまたはペーストタイプの絶縁性接着剤であるとよ
い。
【００１３】
【作用】本考案によれば、成型され、トリミングされた
リード露出型半導体パッケージが基板上に装着され、該
半導体パッケージのチップ内部に内蔵された各種の情報
が各金属ワイヤおよび各基板連結リードを通って基板上
の各部に伝達される。
【００１４】
【実施例】以下、本考案の実施例に対し、図面を用いて
詳細に説明する。
【００１５】図１ないし図３に示したように、本考案に
よるリード露出型半導体パッケージにおいては、両方側
面部位にサイドレール１７，１７′がそれぞれ形成さ
れ、それらサイドレール１７，１７′内方側中央に複数
個の基板連結リード１２ａがそれぞれ所定間隔をおいて
形成され、それら基板連結リード１２ａにそれぞれ連続
して複数個のチップ接続リード１２ｂが形成され、それ
らチップ接続リード１２ｂ端部にそれぞれＶ字型切断溝
１６がエッチングまたはスタンピングにより穿孔形成さ
れ、それらＶ字型切断溝１６と前記両方側サイドレール
１７，１７′間にそれぞれダンパ１８が連結され、それ
ら基板連結リード１２ａおよびチップ接続リード１２ｂ
が該ダンパ１８により両方側サイドレール１７，１７′
にそれぞれ連結されてリードフレームが形成され、該リ
ードフレームの各基板連結リード１２ａ上面に半導体チ
ップ１１が接着剤１３により接着され、該半導体チップ
１１上面の各連結端子（図示されず）と前記各チップ接
続リード１２ｂとがそれぞれ金またはアルミニウムの金
属ワイヤ１４によりワイヤボンディングされ、それら半
導体チップ１、各金属ワイヤ１４、各基板連結リード１
２ａおよび各チップ接続リード１２ｂを包含した所定部
位がモールド樹脂により成型された後、前記Ｖ字型切断
溝１６部位が切断されてリードフレームの外方側が除去
され、リードフレームの各基板連結リード１２ａがパッ
ケージ本体の下面に一様に所定深さ（８．５０ｍｉｌ）
でダウンセットされて露出されるようにリード露出型半
導体パッケージが構成されている。
【００１６】かつ、本考案によるリード露出型半導体パ
ッケージにおいては、成型前にリードフレーム１２の基
板連結リード１２ａとチップ接続リード１２ｂとの連続
部位が所定形状に折曲されて、図１および図２に示した
態様にそれぞれ形成されるが、この場合、図１の第１態
様に比べ、図２の第２態様においては、リードとモール
ド樹脂１５間の接触隙間を通って成型体の内部に侵入す
る水分が一層防止され、リードの接触不良品発生が一層
除去される。
【００１７】また、前記接着剤１３においては、絶縁性
両面テープまたはペーストタイプの絶縁性接着剤が使用
され、熱硬化性の場合は接着された後オーブン（Ｏｖｅ
ｎ）で硬化され、熱可塑性の場合は１７５〜４５０℃の
温度下で硬化される。
【００１８】さらに、成型の後、パッケージ本体外方側
に突出されたリードフレーム部位を切断して除去する
時、前記Ｖ字型切断溝１６が該リードフレームの各チッ
プ接続リード１２ｂに穿孔形成されているため、切断作
業が極めて容易に行なわれ、それらチップ接続リード１
２ｂとモールド樹脂１５間に加わる外力がほとんど省か
れるので、リードの接触不良発生が防止される。
【００１９】このような半導体パッケージは、トレイ
（Ｔｒａｙ）またはチューブ（Ｔｕｂｅ）により電気的
特性試験が行なわれた後、各種セットの基板上に装着さ
れて使用される。
【００２０】
【考案の効果】以上説明したように、本考案によるリー
ド露出型半導体パッケージにおいては、半導体パッケー
ジ本体外方側にリードフレームが突出されずに、基板連
結リードとしてパッケージ本体下面に露出されているた
め、リードフレームのフォーミング工程が省かれ、製品
原価および設備投資費が減少されるという効果がある。
かつ、半導体パッケージ本体外方側にリードフレームが
突成していないため、該リードフレームの撓みにより発
生するリードフレームとモールディング樹脂間の界面分
離および破壊現象がなくなり、製品の信頼性が向上され
るという効果がある。
【００２１】また、半導体パッケージを基板上に装着す
る場合、該半導体パッケージの基板上占有面積が減るた
め、基板上に半導体パッケージを実質的に装着する実装
率が向上されるという効果がある。
【図面の簡単な説明】
【図１】本考案によるリード露出型半導体パッケージの
第１態様を示した縦断面図である。
【図２】本考案によるリード露出型半導体パッケージの
第２態様を示した縦断面図である。
【図３】本考案によるリードフレームを示した平面図で
ある。
【図４】従来のスモールアウトラインＪ−リード型半導
体パッケージの構造を示した縦断面図である。
【図５】従来のスモールアウトライン型半導体パッケー
ジの構造を示した縦断面図である。
【図６】従来のリードフレームを示した平面図である。
【符号の説明】
１１ 半導体チップ １２ リードフレーム １２ａ 基板連結リード １２ｂ チップ接続リード １３ 接着剤 １４ 金属ワイヤ １５ モールド樹脂 １６ Ｖ字型切断溝 １７，１７′ サイドレール １８ ダンパ なお、各図中、同一符号は同一または相当部分を示す。
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/28 - 23/30 H01L 21/56 H01L 23/50

Claims (3)

    (57)【実用新案登録請求の範囲】
  1. 【請求項１】 リード露出型半導体パッケージであっ
    て、 基板連結リード（１２ａ）とチップ接続リード（１２
    ｂ）とから構成され、それら基板連結リード（１２ａ）
    とチップ接続リード（１２ｂ）とは互いに一体型に延長
    されて形成され、前記基板連結リード（１２ａ）が前記
    チップ接続リード（１２ｂ）より下方に位置するように
    ダウンセットされてあるリードと、 前記リードの基板連結リード（１２ａ）の上面に接着剤
    （１３）を介して付着された半導体チップ（１１）と、 前記半導体チップ（１１）の上面と前記チップ接続リー
    ド（１２ｂ）とを連結する金属ワイヤ（１４）と、 前記半導体チップ（１１）、金属ワイヤ（１４）、チッ
    プ接続リード（１２ｂ）の全体および基板連結リード
    （１２ａ）の上面を覆うモールド樹脂（１５）と、 を備え、 前記基板連結リード（１２ａ）の下面が前記モールド樹
    脂（１５）の下面側に露出されてあり、 複数個のリードの上面に半導体チップを載置させてパッ
    ケージしたことを特徴とする 、リード露出型半導体パッ
    ケージ。
  2. 【請求項２】 前記チップ接続リード（１２ｂ）の一側
    端にＶ字型切断溝（１６）が穿孔形成されてあることを
    特徴とする、請求項１記載のリード露出型半導体パッケ
    ージ。
  3. 【請求項３】 前記接着剤（１３）は、絶縁性両面テー
    プまたはペーストタイプの絶縁性接着剤である、請求項
    １記載のリード露出型半導体パッケージ。
JP1993045198U 1992-08-21 1993-08-19 リード露出型半導体パッケージ Expired - Lifetime JP2599748Y2 (ja)

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KR2019920015766U KR0128251Y1 (ko) 1992-08-21 1992-08-21 리드 노출형 반도체 조립장치
KR92U15766 1992-08-21

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JPH0629147U JPH0629147U (ja) 1994-04-15
JP2599748Y2 true JP2599748Y2 (ja) 1999-09-20

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Families Citing this family (165)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594234A (en) * 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
KR0156622B1 (ko) * 1995-04-27 1998-10-15 문정환 반도체 패키지,리드프레임 및 제조방법
KR0179803B1 (ko) * 1995-12-29 1999-03-20 문정환 리드노출형 반도체 패키지
US5866939A (en) * 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
KR100186309B1 (ko) * 1996-05-17 1999-03-20 문정환 적층형 버텀 리드 패키지
KR0179924B1 (ko) * 1996-06-14 1999-03-20 문정환 버텀리드 반도체 패키지
KR100206910B1 (ko) * 1996-06-14 1999-07-01 구본준 반도체 패키지의 디플래쉬 방법
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
KR980006174A (ko) * 1996-06-18 1998-03-30 문정환 버틈 리드 패키지
US5863805A (en) * 1996-07-08 1999-01-26 Industrial Technology Research Institute Method of packaging semiconductor chips based on lead-on-chip (LOC) architecture
KR100201397B1 (ko) * 1996-07-29 1999-06-15 구본준 반도체 패키지 장착용 패키지
JP3026426B2 (ja) * 1996-08-29 2000-03-27 沖電気工業株式会社 樹脂封止型半導体装置とその製造方法及びその金型構造
JP3012816B2 (ja) * 1996-10-22 2000-02-28 松下電子工業株式会社 樹脂封止型半導体装置およびその製造方法
KR100242994B1 (ko) * 1996-12-28 2000-02-01 김영환 버텀리드프레임 및 그를 이용한 버텀리드 반도체 패키지
KR100237051B1 (ko) * 1996-12-28 2000-01-15 김영환 버텀리드 반도체 패키지 및 그 제조 방법
DE19701165C1 (de) * 1997-01-15 1998-04-09 Siemens Ag Chipkartenmodul
JP3877401B2 (ja) 1997-03-10 2007-02-07 三洋電機株式会社 半導体装置の製造方法
JP3022393B2 (ja) * 1997-04-21 2000-03-21 日本電気株式会社 半導体装置およびリードフレームならびに半導体装置の製造方法
US6157074A (en) * 1997-07-16 2000-12-05 Hyundai Electronics Industries Co., Ltd. Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
KR100259359B1 (ko) * 1998-02-10 2000-06-15 김영환 반도체 패키지용 기판 및 반도체 패키지, 그리고 그 제조방법
JP3420057B2 (ja) * 1998-04-28 2003-06-23 株式会社東芝 樹脂封止型半導体装置
US6122822A (en) * 1998-06-23 2000-09-26 Vanguard International Semiconductor Corporation Method for balancing mold flow in encapsulating devices
US6168975B1 (en) * 1998-06-24 2001-01-02 St Assembly Test Services Pte Ltd Method of forming extended lead package
US7071541B1 (en) 1998-06-24 2006-07-04 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6893900B1 (en) 1998-06-24 2005-05-17 Amkor Technology, Inc. Method of making an integrated circuit package
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7030474B1 (en) 1998-06-24 2006-04-18 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7332375B1 (en) 1998-06-24 2008-02-19 Amkor Technology, Inc. Method of making an integrated circuit package
US7112474B1 (en) 1998-06-24 2006-09-26 Amkor Technology, Inc. Method of making an integrated circuit package
US7005326B1 (en) 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
AU1216000A (en) * 1998-10-22 2000-05-08 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
US6448633B1 (en) * 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
KR200309906Y1 (ko) 1999-06-30 2003-04-14 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 리드프레임
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
KR20010037254A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
KR100364978B1 (ko) 1999-10-15 2002-12-16 앰코 테크놀로지 코리아 주식회사 반도체패키지의 와이어 본딩용 클램프 및 히트블록
KR20010056618A (ko) 1999-12-16 2001-07-04 프랑크 제이. 마르쿠치 반도체패키지
KR100355795B1 (ko) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
KR20010037252A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지 제조용 금형
KR20010037247A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
KR100403142B1 (ko) 1999-10-15 2003-10-30 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR100355796B1 (ko) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 반도체패키지용 리드프레임 및 이를 봉지하기 위한 금형 구조
KR100355794B1 (ko) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지
KR100526844B1 (ko) 1999-10-15 2005-11-08 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
KR100379089B1 (ko) 1999-10-15 2003-04-08 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지
US20070176287A1 (en) * 1999-11-05 2007-08-02 Crowley Sean T Thin integrated circuit device packages for improved radio frequency performance
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
TW432557B (en) * 1999-12-14 2001-05-01 Siliconware Precision Industries Co Ltd Chip-scale package and its manufacturing method
US6639308B1 (en) * 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
KR100421774B1 (ko) 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
KR20010058583A (ko) 1999-12-30 2001-07-06 마이클 디. 오브라이언 리드 엔드 그리드 어레이 반도체패키지
KR100592784B1 (ko) * 2000-01-14 2006-06-26 삼성전자주식회사 멀티 칩 패키지
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
US7042068B2 (en) * 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
SG112799A1 (en) 2000-10-09 2005-07-28 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US6686258B2 (en) 2000-11-02 2004-02-03 St Assembly Test Services Ltd. Method of trimming and singulating leaded semiconductor packages
KR20020058209A (ko) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 반도체패키지
KR100731007B1 (ko) * 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지
JP4637380B2 (ja) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 半導体装置
US6967395B1 (en) 2001-03-20 2005-11-22 Amkor Technology, Inc. Mounting for a package containing a chip
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
KR100393448B1 (ko) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US6603196B2 (en) * 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US7064009B1 (en) 2001-04-04 2006-06-20 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US7045883B1 (en) 2001-04-04 2006-05-16 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US6900527B1 (en) 2001-09-19 2005-05-31 Amkor Technology, Inc. Lead-frame method and assembly for interconnecting circuits within a circuit module
US7485952B1 (en) 2001-09-19 2009-02-03 Amkor Technology, Inc. Drop resistant bumpers for fully molded memory cards
US6630726B1 (en) 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
JP2004095572A (ja) * 2002-08-29 2004-03-25 Hitachi Ltd 半導体装置およびその製造方法
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6919620B1 (en) 2002-09-17 2005-07-19 Amkor Technology, Inc. Compact flash memory card with clamshell leadframe
US7361533B1 (en) 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US7190062B1 (en) 2004-06-15 2007-03-13 Amkor Technology, Inc. Embedded leadframe semiconductor package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8129222B2 (en) * 2002-11-27 2012-03-06 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
SG157957A1 (en) * 2003-01-29 2010-01-29 Interplex Qlp Inc Package for integrated circuit die
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6927483B1 (en) 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
US7001799B1 (en) 2003-03-13 2006-02-21 Amkor Technology, Inc. Method of making a leadframe for semiconductor devices
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US6879034B1 (en) 2003-05-01 2005-04-12 Amkor Technology, Inc. Semiconductor package including low temperature co-fired ceramic substrate
US7095103B1 (en) 2003-05-01 2006-08-22 Amkor Technology, Inc. Leadframe based memory card
US7008825B1 (en) 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US6897550B1 (en) 2003-06-11 2005-05-24 Amkor Technology, Inc. Fully-molded leadframe stand-off feature
KR100585100B1 (ko) * 2003-08-23 2006-05-30 삼성전자주식회사 적층 가능한 리드 프레임을 갖는 얇은 반도체 패키지 및그 제조방법
US7245007B1 (en) 2003-09-18 2007-07-17 Amkor Technology, Inc. Exposed lead interposer leadframe package
US6921967B2 (en) * 2003-09-24 2005-07-26 Amkor Technology, Inc. Reinforced die pad support structure
US7138707B1 (en) 2003-10-21 2006-11-21 Amkor Technology, Inc. Semiconductor package including leads and conductive posts for providing increased functionality
US7144517B1 (en) 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
US7211879B1 (en) 2003-11-12 2007-05-01 Amkor Technology, Inc. Semiconductor package with chamfered corners and method of manufacturing the same
US7633140B2 (en) * 2003-12-09 2009-12-15 Alpha And Omega Semiconductor Incorporated Inverted J-lead for power devices
US7057268B1 (en) 2004-01-27 2006-06-06 Amkor Technology, Inc. Cavity case with clip/plug for use on multi-media card
US7091594B1 (en) 2004-01-28 2006-08-15 Amkor Technology, Inc. Leadframe type semiconductor package having reduced inductance and its manufacturing method
US20080003722A1 (en) * 2004-04-15 2008-01-03 Chun David D Transfer mold solution for molded multi-media card
US7202554B1 (en) 2004-08-19 2007-04-10 Amkor Technology, Inc. Semiconductor package and its manufacturing method
US7217991B1 (en) 2004-10-22 2007-05-15 Amkor Technology, Inc. Fan-in leadframe semiconductor package
US7202112B2 (en) * 2004-10-22 2007-04-10 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7517733B2 (en) * 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
JP5217800B2 (ja) 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9564387B2 (en) * 2014-08-28 2017-02-07 UTAC Headquarters Pte. Ltd. Semiconductor package having routing traces therein
FR3104317A1 (fr) * 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160639A (ja) * 1984-01-31 1985-08-22 Nec Corp 半導体装置
JPS62263666A (ja) * 1986-05-10 1987-11-16 Matsushita Electronics Corp 樹脂封止型半導体パツケ−ジ
JPS63152161A (ja) * 1986-12-17 1988-06-24 Hitachi Ltd 半導体装置
JPS63296252A (ja) * 1987-05-27 1988-12-02 Mitsubishi Electric Corp 樹脂封止型半導体装置
US5122860A (en) * 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
US5235207A (en) * 1990-07-20 1993-08-10 Hitachi, Ltd. Semiconductor device
JPH04129252A (ja) * 1990-09-20 1992-04-30 Mitsubishi Electric Corp 半導体パッケージ
US5172214A (en) * 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5250841A (en) * 1992-04-06 1993-10-05 Motorola, Inc. Semiconductor device with test-only leads

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US5428248A (en) 1995-06-27
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