JP2022505518A - 裏面基板薄化を使用して形成された半導体プラグを有する三次元メモリデバイス及びそれを形成するための方法 - Google Patents
裏面基板薄化を使用して形成された半導体プラグを有する三次元メモリデバイス及びそれを形成するための方法 Download PDFInfo
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Abstract
Description
Claims (31)
- 三次元(3D)メモリデバイスであって、
交互に配置された導電層および誘電体層を備えるメモリスタックと、
前記メモリスタックを貫通して垂直に延びるチャネル構造であって、
前記チャネル構造の下部内のチャネルプラグと、
前記チャネル構造の側壁に沿ったメモリフィルムと、
前記メモリフィルムを覆い、前記チャネルプラグと接触している半導体チャネルとを備える、チャネル構造と、
前記メモリスタックの上方にあり、前記半導体チャネルの上方にある、前記半導体チャネルと接触している半導体プラグを備える半導体層とを備える、三次元(3D)メモリデバイス。 - 前記メモリフィルムが、前記チャネル構造の上面および下面に沿って延びない、請求項1に記載の3Dメモリデバイス。
- 前記半導体層が、単結晶シリコンを含む、請求項1または2に記載の3Dメモリデバイス。
- 前記半導体プラグが、エピタキシャル成長させたシリコンプラグである、請求項3に記載の3Dメモリデバイス。
- 前記半導体プラグが、堆積されたポリシリコンプラグまたはケイ化物プラグである、請求項3に記載の3Dメモリデバイス。
- 前記半導体チャネルの上端が、前記半導体プラグの底面と接触している、請求項1から5のいずれか一項に記載の3Dメモリデバイス。
- 前記半導体プラグの底面が、前記メモリスタックの上面の上方にあり、前記半導体プラグの上面が、前記半導体層の上面と同一平面上にある、請求項1から6のいずれか一項に記載の3Dメモリデバイス。
- 前記メモリスタックがその上方に配設される基板と、
前記基板と前記メモリスタックとの間の垂直の接合インターフェースとをさらに備える、請求項1から7のいずれか一項に記載の3Dメモリデバイス。 - 前記半導体層の上方に周辺デバイスをさらに備える、請求項1から8のいずれか一項に記載の3Dメモリデバイス。
- 前記基板と前記メモリスタックとの間に垂直に周辺デバイスをさらに備える、請求項8に記載の3Dメモリデバイス。
- 三次元(3D)メモリデバイスであって、
第1の複数の交互に配置された導電層および誘電体層を備える第1のメモリデッキと、
前記第1のメモリデッキ上のエッチング停止層と、
前記エッチング停止層上に第2の複数の交互に配置された導電層および誘電体層を備える第2のメモリデッキと、
前記第1および第2のメモリデッキならびに前記エッチング停止層を貫通して垂直に延びるチャネル構造と、
前記第2のメモリデッキの上面の上方にあり、前記チャネル構造と接触している半導体プラグとを備える、三次元(3D)メモリデバイス。 - 前記エッチング停止層が、金属または半導体を含む、請求項11に記載の3Dメモリデバイス。
- 前記チャネル構造が、
前記チャネル構造の下部内のチャネルプラグと、
前記チャネル構造の側壁に沿ったメモリフィルムと、
前記メモリフィルムを覆い、前記チャネルプラグおよび前記半導体プラグと接触している半導体チャネルとを備える、請求項11または12に記載の3Dメモリデバイス。 - 前記メモリフィルムが、前記チャネル構造の上面および下面に沿って延びない、請求項13に記載の3Dメモリデバイス。
- 前記半導体チャネルの上端が、前記半導体プラグの底面と接触している、請求項13または14に記載の3Dメモリデバイス。
- 前記半導体プラグが、エピタキシャル成長させたシリコンプラグである、請求項11から15のいずれか一項に記載の3Dメモリデバイス。
- 前記半導体プラグが、堆積されたポリシリコンプラグまたはケイ化物プラグである、請求項11から15のいずれか一項に記載の3Dメモリデバイス。
- 前記第1のメモリデッキがその上方に配置される基板と、
前記基板と前記第1のメモリデッキとの間の垂直の接合インターフェースとを備える、請求項11から17のいずれか一項に記載の3Dメモリデバイス。 - 前記半導体プラグの上方の周辺デバイスをさらに備える、請求項11から18のいずれか一項に記載の3Dメモリデバイス。
- 前記基板と前記第1のメモリデッキとの間に垂直に周辺デバイスをさらに備える、請求項18に記載の3Dメモリデバイス。
- 3次元(3D)メモリデバイスを形成するための方法であって、
交互に配置された犠牲層および誘電体層を備える誘電体スタックを第1の基板の前側に形成することと、
前記誘電体スタックを貫通するチャネル穴を形成することと、
前記チャネル穴の側壁に沿って、かつ底面上にメモリフィルムおよび半導体チャネルを形成することと、
前記誘電体スタック内の前記犠牲層を導電層で置き換えることにより、交互に配置された前記導電層および誘電体層を備えるメモリスタックを形成することと、
前記第1の基板の前記前側が前記第2の基板に向くように前記第1の基板を第2の基板に取り付けることと、
前記第1の基板の裏面から前記第1の基板を薄化して、前記チャネル穴の前記底面上の前記メモリフィルムおよび半導体チャネルの一部を除去することと、
前記薄化された第1の基板内に半導体プラグを形成して、前記半導体チャネルに接触することとを含む、方法。 - 取り付ける前に、前記チャネル穴の上部内にチャネルプラグを形成して、前記半導体チャネルに接触することをさらに含む、請求項21に記載の方法。
- 前記半導体プラグを形成することが、前記薄化された第1の基板内の前記メモリフィルムおよび半導体チャネルの一部を除去してくぼみを形成することを含む、請求項21または22に記載の方法。
- 前記半導体プラグを形成することが、前記くぼみ内に前記半導体プラグを堆積させることをさらに含む、請求項23に記載の方法。
- 前記半導体プラグを形成することが、前記薄化された第1の基板から前記くぼみ内に前記半導体プラグをエピタキシャル成長させることをさらに含む、請求項23に記載の方法。
- 前記誘電体スタックを形成することが、
第1の複数の交互に配置された犠牲層および誘電体層を備える第1の誘電体デッキを前記第1の基板の前記前側に形成することと、
前記第1の誘電体デッキ上にエッチング停止層を形成して、前記第1の誘電体デッキを覆うことと、
第2の複数の交互に配置された犠牲層および誘電体層を備える第2の誘電体デッキを前記エッチング停止層上に形成することとを含む、請求項21から25のいずれか一項に記載の方法。 - 前記チャネル穴を形成することが、
前記第1の誘電体デッキを貫通して垂直に延びる第1の開口部を形成することと、
前記エッチング停止層によって停止されるまで、前記第2の誘電体デッキを貫通して垂直に延びる第2の開口部を形成することと、
前記第1および第2の開口部が接続されて前記チャネル穴を形成するように、前記エッチング停止層の一部を除去することとを含む、請求項26に記載の方法。 - 前記チャネル穴を形成することが、前記第1の基板の一部を貫通して前記チャネル穴のガウジングを形成することを含む、請求項21から27のいずれか一項に記載の方法。
- 前記誘電体スタックを貫通するスリット開口部を形成することと、
前記第1の基板の一部を貫通する前記スリット開口部のガウジングを形成することとを含み、前記チャネル穴のガウジングの深さは、前記スリット開口部のガウジングの深さより大きい、請求項28に記載の方法。 - 取り付ける前に、前記第2の基板上に周辺デバイスを形成することをさらに含む、請求項21から29のいずれか一項に記載の方法。
- 前記半導体プラグを形成した後、前記薄化された第1の基板の上方に周辺デバイスを形成することをさらに含む、請求項21から29のいずれか一項に記載の方法。
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CN111403413A (zh) | 2020-07-10 |
US10679985B2 (en) | 2020-06-09 |
KR102573353B1 (ko) | 2023-08-30 |
TW202017160A (zh) | 2020-05-01 |
TWI670837B (zh) | 2019-09-01 |
US20200126974A1 (en) | 2020-04-23 |
CN109496355B (zh) | 2020-03-27 |
WO2020082227A1 (en) | 2020-04-30 |
KR20210028249A (ko) | 2021-03-11 |
CN109496355A (zh) | 2019-03-19 |
JP7190564B2 (ja) | 2022-12-15 |
EP3830872A1 (en) | 2021-06-09 |
CN111403413B (zh) | 2022-06-14 |
EP3830872A4 (en) | 2022-03-16 |
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