JP2022177252A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 248
- 239000011347 resin Substances 0.000 claims abstract description 143
- 229920005989 resin Polymers 0.000 claims abstract description 143
- 238000007789 sealing Methods 0.000 claims abstract description 62
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 39
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- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
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- 230000002500 effect on skin Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
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- 230000017525 heat dissipation Effects 0.000 description 1
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- 230000037431 insertion Effects 0.000 description 1
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- 230000035515 penetration Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
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- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/495—Lead-frames or other flat leads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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Abstract
Description
これらの組み合わせによって形成されたものでもよい。パッシベーション膜14から、ゲート電極11のパッド電極部111およびソース電極12がともに露出している。
1 :半導体素子
10a :素子主面
10b :素子裏面
11 :ゲート電極
111 :パッド電極部
112 :フィンガー電極部
12 :ソース電極
121 :パッド電極部
122 :フィンガー電極部
13 :ドレイン電極
131 :パッド電極部
132 :フィンガー電極部
14 :パッシベーション膜
2 :封止樹脂
21 :樹脂主面
22 :樹脂裏面
23 :樹脂側面
25 :樹脂凹部
25a :樹脂凹部底面
25b :樹脂凹部側面
3 :第1リード
31 :第1パッド部
311 :第1パッド主面
312 :第1パッド接合面
313 :凹部
313a :凹部内面
313b :凹部底面
314 :貫通孔
314a :貫通孔内面
32 :第1露出部
32a :第1先端面
321 :第1端子部
322 :第1屈曲部
33 :第1連結部
34 :帯状部
4 :第2リード
41 :第2パッド部
411 :第2パッド主面
412 :第2パッド接合面
42 :第2露出部
42a :第2先端面
421 :第2端子部
422 :第2屈曲部
43 :第2連結部
5 :第3リード
50a :搭載面
50b :実装面
51 :貫通孔
52 :第3露出部
521 :露出側面
521a :露出側面第1部
521b :露出側面第2部
6 :導電性接合材
61 :第1接合材
62 :第2接合材
63 :第3接合材
64 :第4接合材
7,7’ :ストラップ部材
71 :第1クリップ接合部
711 :ストラップ主面
712 :ストラップ接合面
713 :凹部
72 :第2クリップ接合部
73 :屈曲部
Claims (18)
- 厚さ方向において互いに反対側を向く素子主面および素子裏面を有し、前記素子主面に第1電極および第2電極が形成された半導体素子と、
前記第1電極に電気的に接続された第1導電部材と、
前記第2電極に電気的に接続された第2導電部材と、
前記第1導電部材の一部、前記第2導電部材の一部、および、前記半導体素子を覆う封止樹脂と、を備えており、
前記第1導電部材は、前記厚さ方向に見て前記半導体素子のほぼ全域に重なる大きさであり、且つ、第1パッド部を含んでおり、
前記第1パッド部は、前記第1電極に接合された接合面および前記厚さ方向において前記接合面と反対側を向く第1パッド主面を有しており、さらに、前記接合面から前記第1パッド主面に向かって広がる内面を有し、かつ、前記第1電極に接合されない非接合部を含んでいる、
ことを特徴とする半導体装置。 - 前記第2電極は、前記第2導電部材が接合されたパッド電極部と、前記第2電極の内部抵抗を低減するためのフィンガー電極部とを有しており、
前記非接合部は、前記厚さ方向に見て、前記フィンガー電極部に重なる、
請求項1に記載の半導体装置。 - 前記半導体素子は、前記フィンガー電極部を覆う絶縁膜を有する、
請求項2に記載の半導体装置。 - 前記半導体素子は、前記厚さ方向に見て0.05~0.3mm角である、
請求項2または請求項3のいずれか一項に記載の半導体装置。 - 前記第1導電部材は、前記厚さ方向に見て前記封止樹脂から突き出た第1露出部と、前記封止樹脂に覆われ、かつ、前記第1パッド部および前記第1露出部に繋がる第1連結部と、をさらに含んでいる、
請求項1ないし請求項4のいずれか一項に記載の半導体装置。 - 前記半導体素子から離間するリードをさらに備え、
前記リードは、前記厚さ方向に見て前記封止樹脂から突き出た第1露出部と、前記封止樹脂に覆われたインナー部と、前記インナー部および前記第1露出部に繋がる第1連結部とを含み、
前記第1導電部材は、前記インナー部に接合された接合部を含む、
請求項1ないし請求項4のいずれか一項に記載の半導体装置。 - 前記第1露出部は、前記第1連結部に繋がり、かつ、前記厚さ方向に屈曲した第1屈曲部、および、前記第1屈曲部に繋がる第1端子部を含んでいる、
請求項5または請求項6に記載の半導体装置。 - 前記半導体素子が搭載された第3導電部材をさらに備えており、
前記半導体素子は、前記素子裏面に第3電極が形成されており、
前記第3導電部材は、前記第3電極に電気的に接続している、
請求項7に記載の半導体装置。 - 前記封止樹脂は、前記素子裏面と同じ方向を向く樹脂裏面を有しており、
前記第3導電部材は、前記素子裏面と同じ方向を向き、かつ、前記樹脂裏面から露出する実装面を有しており、
前記第1端子部は、前記厚さ方向に直交する第1方向に見て、前記第3導電部材に重なる、
請求項8に記載の半導体装置。 - 前記第2導電部材は、前記第2電極に接合された第2パッド部と、前記厚さ方向に見て、前記封止樹脂から突き出た第2露出部と、前記封止樹脂に覆われ、かつ、前記第2パッド部および前記第2露出部に繋がる第2連結部と、を含んでいる、
請求項9に記載の半導体装置。 - 前記第2露出部は、前記第2連結部に繋がり、かつ、前記厚さ方向に屈曲した第2屈曲部、および、前記第2屈曲部に繋がる第2端子部を含んでいる、
請求項10に記載の半導体装置。 - 前記第2端子部は、前記第1方向に見て、前記第3導電部材に重なる、
請求項11に記載の半導体装置。 - 前記非接合部は、前記内面に繋がり、かつ、前記接合面と同じ方向を向く底面をさらに含む、
請求項1ないし請求項12のいずれか一項に記載の半導体装置。 - 前記非接合部は、各々が前記厚さ方向に直交する第1方向に延びており、かつ、前記厚さ方向および前記第1方向の両方に直交する第2方向に並んだ複数の凹部である、
請求項13に記載の半導体装置。 - 前記複数の凹部はそれぞれ、前記第1パッド部の前記第1方向の一方側の端縁から前記第1方向の他方側の端縁まで繋がる、
請求項14に記載の半導体装置。 - 前記第1パッド主面は、少なくとも一部が前記封止樹脂から露出する、
請求項1ないし請求項15のいずれか一項に記載の半導体装置。 - 前記封止樹脂は、前記素子主面と同じ方向を向く樹脂主面および当該樹脂主面から窪んだ樹脂凹部を有しており、
前記樹脂凹部は、樹脂凹部底面、および、当該樹脂凹部底面と前記樹脂主面とに繋がる樹脂凹部側面を有しており、
前記樹脂凹部底面と前記第1パッド主面とが面一である、
請求項16に記載の半導体装置。 - 前記半導体素子は、パワーMOSFETであり、
前記第1電極は、ソース電極であり、
前記第2電極は、ゲート電極である、
請求項1ないし請求項17のいずれか一項に記載の半導体装置。
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Cited By (2)
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WO2024095097A1 (en) | 2022-11-04 | 2024-05-10 | Ricoh Company, Ltd. | Image-forming lens, interchangeable lens, image-capturing apparatus, and information processing apparatus |
WO2024116899A1 (ja) * | 2022-12-02 | 2024-06-06 | ローム株式会社 | 半導体装置、および半導体装置の製造方法 |
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JP7150461B2 (ja) * | 2018-04-24 | 2022-10-11 | ローム株式会社 | 半導体装置 |
US11069600B2 (en) * | 2019-05-24 | 2021-07-20 | Infineon Technologies Ag | Semiconductor package with space efficient lead and die pad design |
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