JP2021521629A5 - - Google Patents

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Publication number
JP2021521629A5
JP2021521629A5 JP2020554400A JP2020554400A JP2021521629A5 JP 2021521629 A5 JP2021521629 A5 JP 2021521629A5 JP 2020554400 A JP2020554400 A JP 2020554400A JP 2020554400 A JP2020554400 A JP 2020554400A JP 2021521629 A5 JP2021521629 A5 JP 2021521629A5
Authority
JP
Japan
Prior art keywords
layer
thickness
semiconductor substrate
oxide
forming
Prior art date
Application number
JP2020554400A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021521629A (ja
JPWO2019195435A5 (https=
Filing date
Publication date
Priority claimed from US15/944,550 external-priority patent/US10566200B2/en
Application filed filed Critical
Publication of JP2021521629A publication Critical patent/JP2021521629A/ja
Publication of JP2021521629A5 publication Critical patent/JP2021521629A5/ja
Publication of JPWO2019195435A5 publication Critical patent/JPWO2019195435A5/ja
Pending legal-status Critical Current

Links

JP2020554400A 2018-04-03 2019-04-03 トランジスタを製造する方法 Pending JP2021521629A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/944,550 US10566200B2 (en) 2018-04-03 2018-04-03 Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings
US15/944,550 2018-04-03
PCT/US2019/025599 WO2019195435A1 (en) 2018-04-03 2019-04-03 Method of fabricating transistors

Publications (3)

Publication Number Publication Date
JP2021521629A JP2021521629A (ja) 2021-08-26
JP2021521629A5 true JP2021521629A5 (https=) 2022-04-08
JPWO2019195435A5 JPWO2019195435A5 (https=) 2022-04-08

Family

ID=68055429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020554400A Pending JP2021521629A (ja) 2018-04-03 2019-04-03 トランジスタを製造する方法

Country Status (5)

Country Link
US (1) US10566200B2 (https=)
EP (1) EP3776637A4 (https=)
JP (1) JP2021521629A (https=)
CN (1) CN112074932A (https=)
WO (1) WO2019195435A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11227926B2 (en) * 2020-06-01 2022-01-18 Nanya Technology Corporation Semiconductor device and method for fabricating the same
CN116417404B (zh) * 2021-12-30 2026-04-14 无锡华润上华科技有限公司 双栅结构、场氧结构及半导体器件的制造方法

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KR100225411B1 (ko) * 1997-03-24 1999-10-15 김덕중 LDMOS(a lateral double-diffused MOS) 트랜지스터 소자 및 그의 제조 방법
JPH1167904A (ja) * 1997-08-15 1999-03-09 Hitachi Ltd 半導体集積回路装置の製造方法
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JP2000353804A (ja) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
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JP2005123314A (ja) * 2003-10-15 2005-05-12 Semiconductor Leading Edge Technologies Inc パターン形成方法
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KR20060070334A (ko) 2004-12-20 2006-06-23 삼성전자주식회사 박막 트랜지스터 표시판의 제조 방법
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