WO2014161463A1 - 半导体器件栅氧化层的形成方法 - Google Patents

半导体器件栅氧化层的形成方法 Download PDF

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WO2014161463A1
WO2014161463A1 PCT/CN2014/074496 CN2014074496W WO2014161463A1 WO 2014161463 A1 WO2014161463 A1 WO 2014161463A1 CN 2014074496 W CN2014074496 W CN 2014074496W WO 2014161463 A1 WO2014161463 A1 WO 2014161463A1
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oxide layer
gate
polysilicon
forming
semiconductor device
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PCT/CN2014/074496
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French (fr)
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李健
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a gate oxide layer of a semiconductor device The method of formation.
  • the manufacturing process of a high voltage device below 0.18 microns has a thicker gate silicon oxide (>400 angstroms) to Achieve higher operating voltages.
  • the conventional high voltage device gate forming step generally includes: gate oxidation Silicon deposition, polysilicon deposition, polysilicon etching, polysilicon sidewall oxidation, etc. 1A to 1C are shown.
  • the device structure of FIG. 1A includes a silicon substrate 110, a silicon oxide layer 120, and polysilicon. 130. After etching the source and drain oxide layers on the structure shown in FIG. 1A, the structure shown in FIG. 1B is obtained. After the silicon layer 120 is etched, the source and drain oxide layers 124 and the gate oxide layer 122 are obtained; again, as shown in FIG. 1B.
  • the structure is thermally oxidized to grow such that the sidewall of the polysilicon 130 as the gate grows the sidewall oxide layer 132, The structure shown in Fig. 1C is obtained.
  • the uniformity of the gate oxide layer 122 is not good, and the gate near the middle of the polysilicon 130
  • the thickness of the electrode oxide layer 122 is relatively normal, and the gate oxide layer 122 near the left and right ends of the polysilicon 130 is more than It is desirable to have a thick thickness. Therefore, the uniformity of the overall thickness of the gate oxide layer 122 is poor, and the device is unstable. set.
  • a method of forming a gate oxide layer of a semiconductor device comprising the steps of: forming an oxide on a substrate a layer; depositing polysilicon on the oxide layer; photolithography and etching the polysilicon to form polysilicon a gate; thermally oxidizing sidewalls of the polysilicon gate, and growing silicon oxide on the sidewall;
  • the oxide layer is photolithographically and etched to thin a portion of the oxide layer on the source and drain.
  • the step of growing silicon oxide on the sidewall requires oxidation Overgrowth of silicon; in the step of photolithography and etching the oxide layer, the overgrown silicon oxide is etched Thinning to restore the desired thickness.
  • the silicon oxide grown in the step of growing silicon oxide on the sidewall is thick The degree is from 120% to 200% of the desired thickness, wherein the silica is silica.
  • the desired thickness is 50 angstroms
  • the silicon oxide is grown on the sidewall
  • the thickness of the silicon oxide grown in the step was 80 angstroms.
  • the pair The thickness of the oxide layer is greater than 400 angstroms prior to the step of thermally oxidizing the sidewalls of the polysilicon gate.
  • the step of forming an oxide layer on the substrate is by using a deposition process
  • the oxide layer is formed, and the composition of the oxide layer is silicon dioxide.
  • the method for forming a gate oxide layer of the above semiconductor device changes the conventional process sequence in polysilicon After the etching, the oxidation of the sidewall of the polysilicon gate is performed first, and then the etching of the oxide layer of the high voltage device region is performed. by When the sidewall is oxidized, the oxide layer is located under the polysilicon gate and the portion above the source and drain The thickness is substantially flat, so the portion of the oxide layer under the polysilicon gate is not exposed to the outside world.
  • Oxidation of the sidewall of the polysilicon gate oxygen will only react with the sidewall of the polysilicon gate to form sidewall oxidation Layer, instead of infiltrating into the polysilicon at both ends of the gate oxide layer as in the conventional art, causing longitudinal
  • the oxidation reaction causes the gate oxide layer to become thick. Therefore, the uniformity of the thickness of the gate oxide layer is ensured, and the improvement is greatly improved.
  • the lateral uniformity of the gate oxide layer makes the operation of the high voltage device more stable.
  • FIG. 1A to 1C are cross-sections of a high voltage device region of a conventional semiconductor high voltage device during fabrication.
  • FIG. 2 is a flow chart showing a method of forming a gate oxide layer of a semiconductor device in an embodiment
  • 3A-3D illustrate a device in which a method of forming a gate oxide layer of a semiconductor device is used in an embodiment.
  • the inventors have found through research and analysis that in the manufacturing process of conventional high voltage devices, After the silicon oxide layer 120 of the high voltage device region is etched, the source and drain silicon oxides are already thin, and the gate oxide layer The left and right ends of 122 are exposed.
  • the present invention provides a semiconductor device gate oxide
  • the formation method of the layer includes the following steps:
  • the invention is mainly directed to a high voltage device having a thick gate oxide layer (greater than 400 angstroms).
  • a high voltage device is formed on the substrate 210 by a deposition process.
  • the oxide layer 220 of the device region, the composition of the oxide layer 220 is silicon oxide (eg, silicon dioxide), and the substrate 210
  • the composition is silicon.
  • other processes known to those skilled in the art may also be used.
  • An oxide layer such as thermal oxidation growth or the like.
  • polysilicon as a gate electrode is deposited thereon, and a chemical vapor deposition can be used.
  • a polysilicon gate 230 is formed after polysilicon etching.
  • the sidewall of the polysilicon gate 230 is oxidized to silicon oxide to form a sidewall oxide layer 232.
  • the oxide layer 220 of the high voltage device region is photolithographically and etched, and the oxide layer is 220 bits.
  • the portions on the source and the drain on both sides of the polysilicon gate 230 are etched and thinned to form source and drain oxygen.
  • the layer 224; the thickness of the portion of the oxide layer 220 under the polysilicon gate 230 remains unchanged as the gate oxide Layer 222.
  • the method for forming a gate oxide layer of the above semiconductor device changes the conventional process sequence in polysilicon After the etching, the oxidation of the sidewall of the polysilicon gate 230 is performed first, and then the high-voltage device region oxide layer 220 is formed. Etching. When the sidewall is oxidized, the portion of the oxide layer 220 under the polysilicon gate 230 is still thick (large At 400 angstroms, the thickness of the portion above the source and drain is substantially flat, so the oxide layer 220 is located at The portion under the crystalline silicon gate 230 is not exposed to the outside, and the oxygen on the sidewall of the polysilicon gate 230 is performed.
  • Oxygen will only react with the sidewalls of the polysilicon gate 230 to form the sidewall oxide layer 232, unlike conventional The same technology penetrates the two ends of the gate oxide layer and contacts the polysilicon, causing the vertical oxidation reaction to cause the gate.
  • the oxide layer becomes thick. Therefore, the uniformity of the thickness of the gate oxide layer 222 is ensured, and the gate oxide layer 222 is greatly improved.
  • the lateral uniformity makes the high voltage device work more stable.
  • the oxidation is performed in step S140, that is, by increasing the oxidation time and the like.
  • the thickness is obtained in excess of the desired thickness of the sidewall oxide layer 232. This is because in actual production
  • the sidewall oxide layer 232 will be thinned by the influence of the etching in step S150, and therefore needs to be at S140. Compensating for the loss of the sidewall oxide layer 232 at step S150 in the step, such that the sidewalls excessively grown in S140
  • the oxide layer 232 is just etched away in S150.
  • the amount of over-growth of sidewall oxide layer 232 in S140 is S150
  • the sidewall oxygen grown in step S140 The thickness of the layer 232 (lateral) is 120% to 200% of the desired thickness of the final sidewall oxide layer 232 (ie, The amount grows by 20% to 100% of the thickness).
  • the sidewalls grown in step S140 are oxidized.
  • the layer 232 has a thickness of 80 angstroms and remains 50 angstroms after the etching in step S150 (i.e., a desired thickness of 50 angstroms).

Abstract

本发明公开了一种半导体器件栅氧化层的形成方法，包括：在衬底上形成氧化层；在所述氧化层上沉积多晶硅；对所述多晶硅进行光刻和刻蚀，形成多晶硅栅极；对所述多晶硅栅极的侧壁进行热氧化，在所述侧壁上生长氧化硅；对所述氧化层进行光刻和刻蚀，将位于源极和漏极上的部分所述氧化层进行减薄。本发明能够保证高压器件栅氧化层厚度的均匀性，大大改善了栅氧化层的横向均匀度，使高压器件工作更加稳定。

Description

半导体器件栅氧化层的形成方法 技术领域
本发明涉及半导体器件的制造方法，特别是涉及一种半导体器件栅氧化层 的形成方法。
背景技术
0.18微米以下的高压器件的制造过程，其栅极氧化硅较厚（>400埃），以 实现较高的工作电压。而传统的高压器件栅极的形成步骤一般包括：栅极氧化 硅的沉积，多晶硅的沉积，多晶硅的刻蚀，多晶硅侧壁的氧化等几个部分，如 图1A～图1C所示。图1A的器件结构包括硅衬底110、氧化硅层120及多晶硅 130，对图1A所示的结构进行源、漏极氧化层的刻蚀后得到图1B所示结构，氧 化硅层120刻蚀后得到源、漏极氧化层124和栅极氧化层122；再对图1B所示 结构进行热氧化生长，使得作为栅极的多晶硅130的侧壁长出侧壁氧化层132， 得到图1C所示结构。
从图1C可以看到栅极氧化层122的均匀性不好，靠近多晶硅130中部的栅 极氧化层122厚度比较正常，靠近多晶硅130左右两端的栅极氧化层122则比 期望厚度要厚。因此，栅极氧化层122整体厚度的均匀性较差，器件工作不稳 定。
发明内容
基于此，为了解决栅极氧化层整体厚度的均匀性较差的问题，有必要提供 一种半导体器件栅氧化层的形成方法。
一种半导体器件栅氧化层的形成方法，包括下列步骤：在衬底上形成氧化 层；在所述氧化层上沉积多晶硅；对所述多晶硅进行光刻和刻蚀，形成多晶硅 栅极；对所述多晶硅栅极的侧壁进行热氧化，在所述侧壁上生长氧化硅；对所 述氧化层进行光刻和刻蚀，将位于源极和漏极上的部分所述氧化层进行减薄。
在其中一个实施例中，所述在侧壁上生长氧化硅的步骤中，需要进行氧化 硅的过生长；所述对氧化层进行光刻和刻蚀的步骤中，过生长的氧化硅被刻蚀 减薄从而恢复期望厚度。
在其中一个实施例中，所述在侧壁上生长氧化硅的步骤中生长的氧化硅厚 度为所述期望厚度的120%～200%，其中所述氧化硅为二氧化硅。
在其中一个实施例中，所述期望厚度为50埃，所述在侧壁上生长氧化硅的 步骤中生长的氧化硅厚度为80埃。
在其中一个实施例中，所述对多晶硅进行光刻和刻蚀的步骤之后，所述对 多晶硅栅极的侧壁进行热氧化的步骤之前，所述氧化层的厚度大于400埃。
在其中一个实施例中，所述在衬底上形成氧化层的步骤，是采用沉积工艺 形成所述氧化层，所述氧化层的成分为二氧化硅。
上述半导体器件栅氧化层的形成方法，改变了传统的工艺顺序，在多晶硅 刻蚀之后，先进行多晶硅栅极侧壁的氧化，再做高压器件区氧化层的刻蚀。由 于侧壁氧化时，氧化层位于多晶硅栅极下方的部分和位于源、漏极上方的部分 厚度基本持平，因此氧化层位于多晶硅栅极下方的部分没有暴露给外界，这时 进行多晶硅栅极侧壁的氧化，氧气只会和多晶硅栅极的侧壁反应形成侧壁氧化 层，而不会像传统技术一样沿栅极氧化层两端渗入而与多晶硅接触，造成纵向 氧化反应导致栅极氧化层变厚。因此保证了栅氧化层厚度的均匀性，大大改善 了栅氧化层的横向均匀度，使高压器件工作更加稳定。
附图说明
图1A～图1C为一种传统的半导体高压器件在制造过程中高压器件区的剖面 示意图；
图2为一实施例中半导体器件栅氧化层的形成方法的流程图；
图3A～图3D为一实施例中采用半导体器件栅氧化层的形成方法的器件在制 造过程中高压器件区的剖面示意图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发 明的具体实施方式做详细的说明。
参见图1A～图1C，发明人经研究分析发现：在传统高压器件的制造过程， 高压器件区的氧化硅层120刻蚀之后，源、漏极氧化硅已经很薄，栅极氧化层 122的左右两端暴露在外。在接下来的氧化生长侧壁氧化层132步骤，多晶硅 130侧壁被氧化生成氧化硅的同时，由于栅极氧化层122不够致密而且暴露在外， 氧化步骤中的氧气会渗入栅极氧化层122的左右两端，并在纵向上与多晶硅130 反应，造成氧化硅的纵向生长，导致多晶硅130左右两侧的栅极氧化层122变 厚。
为了改善高压器件中栅氧化层的均匀性，本发明提供一种半导体器件栅氧 化层的形成方法，如图2所示，包括下列步骤：
S110，在衬底上形成氧化层。
本发明主要针对的是高压器件，其具有栅氧化层较厚（大于400埃）的特 征，既可以是独立的高压器件，也可以是一个器件上包括高压器件区和低压器 件区。请参见图3A，在本实施例中，是在衬底210上通过沉积工艺形成高压器 件区的氧化层220，氧化层220的成分为氧化硅（如：二氧化硅），衬底210的 成分为硅。在其它实施例中，也可以采用本领域技术人员习知的其它工艺形成 氧化层，例如热氧化生长等。
S120，在氧化层上沉积多晶硅。
形成氧化层220后，在其上沉积作为栅极的多晶硅，可以采用化学气相沉 积（CVD）等本领域技术人员习知的沉积方法。
S130，对沉积的多晶硅进行光刻和刻蚀，形成多晶硅栅极。
请参见图3B，多晶硅刻蚀后形成多晶硅栅极230。
S140，对多晶硅栅极的侧壁进行热氧化，在侧壁上生长氧化硅。
请参见图3C，多晶硅栅极230的侧壁被氧化成氧化硅，生成侧壁氧化层232。
S150，对氧化层进行光刻和刻蚀，将位于源极和漏极上的部分氧化层进行 减薄。
请参见图3D，对高压器件区的氧化层220进行光刻和刻蚀，氧化层220位 于多晶硅栅极230两侧的源极和漏极上的部分被刻蚀后减薄，形成源、漏极氧 化层224；氧化层220位于多晶硅栅极230下方的部分厚度保持不变，作为栅氧 化层222。
上述半导体器件栅氧化层的形成方法，改变了传统的工艺顺序，在多晶硅 刻蚀之后，先进行多晶硅栅极230侧壁的氧化，再做高压器件区氧化层220的 刻蚀。由于侧壁氧化时，氧化层220位于多晶硅栅极230下方的部分还很厚（大 于400埃），和位于源、漏极上方部分的厚度基本持平，因此氧化层220位于多 晶硅栅极230下方的部分没有暴露给外界，这时进行多晶硅栅极230侧壁的氧 化，氧气只会和多晶硅栅极230的侧壁反应形成侧壁氧化层232，而不会像传统 技术一样沿栅极氧化层两端渗入而与多晶硅接触，造成纵向氧化反应导致栅极 氧化层变厚。因此保证了栅氧化层222厚度的均匀性，大大改善了栅氧化层222 的横向均匀度，使高压器件工作更加稳定。
在优选的实施例中，步骤S140中要进行过氧化，即通过增加氧化时间等方 式，获得比侧壁氧化层232的期望厚度过量的厚度。这是因为在实际生产中发 现侧壁氧化层232会在步骤S150中受到刻蚀的影响被减薄，因此需要在S140 步骤中补偿侧壁氧化层232在步骤S150的损耗，使得S140中过量生长的侧壁 氧化层232在S150中正好被腐蚀掉。S140中侧壁氧化层232过生长的量与S150 中刻蚀的工艺、参数等有关，在其中一个实施例中，步骤S140中生长的侧壁氧 化层232（横向的）厚度为最终侧壁氧化层232期望厚度的120%～200%（即过 量生长20%～100%的厚度）。在优选的实施例中，步骤S140中生长的侧壁氧化 层232厚度为80埃，步骤S150中刻蚀完成后剩余50埃（即期望厚度为50埃）。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细， 但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域 的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和 改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附 权利要求为准。

Claims (6)

  1. 一种半导体器件栅氧化层的形成方法，其特征在于，其包括：
    在衬底上形成氧化层；
    在所述氧化层上沉积多晶硅；
    对所述多晶硅进行光刻和刻蚀，形成多晶硅栅极；
    对所述多晶硅栅极的侧壁进行热氧化，在所述侧壁上生长氧化硅；
    对所述氧化层进行光刻和刻蚀，将位于源极和漏极上的部分所述氧化层进 行减薄。
  2. 根据权利要求1所述的半导体器件栅氧化层的形成方法，其特征在于， 所述在侧壁上生长氧化硅的步骤中，需要进行氧化硅的过生长；所述对氧化层 进行光刻和刻蚀的步骤中，过生长的氧化硅被刻蚀减薄从而恢复期望厚度。
  3. 根据权利要求2所述的半导体器件栅氧化层的形成方法，其特征在于， 所述在侧壁上生长氧化硅的步骤中生长的氧化硅厚度为所述期望厚度的 120%～200%，其中所述氧化硅为二氧化硅。
  4. 根据权利要求3所述的半导体器件栅氧化层的形成方法，其特征在于， 所述期望厚度为50埃，所述在侧壁上生长氧化硅的步骤中生长的氧化硅厚度为 80埃。
  5. 根据权利要求1所述的半导体器件栅氧化层的形成方法，其特征在于， 所述对多晶硅进行光刻和刻蚀的步骤之后，所述对多晶硅栅极的侧壁进行热氧 化的步骤之前，所述氧化层的厚度大于400埃。
  6. 根据权利要求1所述的半导体器件栅氧化层的形成方法，其特征在于， 所述在衬底上形成氧化层的步骤，是采用沉积工艺形成所述氧化层，所述氧化 层的成分为二氧化硅。
PCT/CN2014/074496 2013-04-02 2014-03-31 半导体器件栅氧化层的形成方法 WO2014161463A1 (zh)

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