CN112074932A - 制造晶体管的方法 - Google Patents
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Abstract
一种制造晶体管的方法(500)包括:在半导体衬底上形成(502)第一电介质层;在第一电介质层上沉积(504)阻挡层;在阻挡层上沉积(506)抗反射涂层;沉积(508)及使光致抗蚀剂层中的图案暴露(510)于辐射,然后蚀刻(512)以提供开口;蚀刻(514)开口下方的抗反射涂层的一部分;蚀刻(516)开口下方的阻挡层的一部分以暴露第一电介质层的一部分;提供(518)环境氧化剂以生长氧化区域,然后移除(520)阻挡层;在移除阻挡层之后,将掺杂剂植入(522)到半导体衬底中;在将掺杂剂植入到半导体衬底中之后移除(524)第一电介质层;及在移除第一电介质层之后形成(526)第二电介质层,其中所述氧化物区域生长为比第二电介质层厚。
Description
背景技术
在许多应用中,晶体管应具有相对低的比电阻。对于一些场效应晶体管,例如漏极延伸金属氧化物半导体(DEMOS)晶体管,增加栅极氧化物部分上方的氧化物厚度可降低比电阻。
发明内容
在至少一个实例中,一种制造晶体管的方法包含:在半导体衬底上形成第一电介质层;在所述第一电介质层上沉积阻挡层;在所述阻挡层上沉积抗反射涂层;沉积光致抗蚀剂层;使光致抗蚀剂层中的图案暴露于辐射;根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;蚀刻光致抗蚀剂层中的开口下方的抗反射涂层的一部分;蚀刻开口下方的阻挡层的一部分以暴露第一电介质层的一部分;在蚀刻开口下方的阻挡层的所述部分之后提供环境氧化剂,以生长氧化物区域;在提供环境氧化剂之后移除阻挡层;在移除阻挡层之后,将掺杂剂植入到半导体衬底中;在将掺杂剂植入到半导体衬底中之后移除第一电介质层;及在移除所述第一电介质层之后形成第二电介质层,其中所述氧化物区域生长为比所述第二电介质层厚。
在至少一个实例中,一种制造晶体管的方法包含:在半导体衬底上形成牺牲氧化物层;在牺牲氧化物层上沉积氮化硅层;在氮化硅层上沉积抗反射涂层;沉积光致抗蚀剂层;使光致抗蚀剂层中的图案暴露于辐射;根据所述图案蚀刻光致抗蚀剂层以在光致抗蚀剂层中提供开口;蚀刻开口下方的抗反射涂层的一部分;蚀刻开口下方的氮化硅层的一部分以暴露牺牲氧化物层的一部分;及在牺牲氧化物层的暴露部分上生长氧化物区域;在生长氧化物区域之后移除氮化硅层;在移除氮化硅层之后,将掺杂剂植入到半导体衬底中;在将掺杂剂植入到半导体衬底中之后移除牺牲氧化物层;及在移除牺牲氧化物层之后在半导体衬底上形成栅极氧化物层,其中所述氧化物区域生长到比栅极氧化物层的厚度更大的厚度。
在至少一个实例中,一种制造晶体管的方法包含:在半导体衬底上形成牺牲氧化物层;在牺牲氧化物层上沉积氮化硅层;沉积光致抗蚀剂层;使光致抗蚀剂层中的图案暴露于辐射;根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;蚀刻开口下方的氮化硅层的一部分以暴露牺牲氧化物层的一部分;在牺牲氧化物层的暴露部分上生长至少400埃厚的氧化物区域;在生长氧化物区域之后移除氮化硅层;在移除氮化硅层之后,将掺杂剂植入到半导体衬底中,以在半导体衬底中形成漏极区域;在将掺杂剂植入到半导体衬底中之后移除牺牲氧化物层;及在移除牺牲氧化物层之后在半导体衬底上形成栅极氧化物层,所述栅极氧化物层具有小于400埃的厚度。
附图说明
图1展示在各种实例中的晶体管。
图2展示在各种实例中具有数个层的半导体衬底。
图3展示在各种实例中蚀刻之后的硅衬底。
图4展示在各种实例中具有氧化物区域的硅衬底。
图5展示在各种实例中的工艺流程。
图6展示在各种实例中的两个晶体管。
具体实施方式
在所描述的实施例中,制造晶体管(例如DEMOS晶体管)的方法包括在晶体管栅极下方生长厚氧化物,其中工艺步骤可并入到标准双极互补金属氧化物半导体(BiCMOS)工艺流程中。
图1展示未按比例绘制的实例晶体管100的横截面图。在图1的实例中,实例晶体管100是DEMOS晶体管。漏极区域104及源极区域106在半导体衬底102中形成。在图1的实例中,半导体衬底102是硅晶体,且实例晶体管100是n型DEMOS晶体管,其中漏极区域104及源极区域106每一者是高掺杂n型区域。源极区域106在轻掺杂p型阱108内形成,且漏极区域104通过轻掺杂n型区域110延伸。
电介质层112在半导体衬底102上形成。电介质层112通常是二氧化硅,且电介质层112被称为栅极氧化物层112。栅极114在栅极氧化物层112上方形成。栅极114可包含多晶硅。氧化物区域116生长在半导体衬底102上且进入所述半导体衬底102中。氧化物区域116邻近于漏极区域104且在栅极114下方,且氧化物区域116比电介质层112厚。氧化物区域116可包含二氧化硅。氧化物区域116的存在提供到栅极114的提升。高掺杂p型区域118用作实例晶体管100的主体接触。
当实例晶体管100导通,使得栅极114下方的沟道处于反转模式时,大多数载流子的沟道电流(例如,n型沟道的电子)从源极区域106流向漏极区域104。氧化物区域116的存在影响沟道电流的路径。氧化物区域116进入沟道的相对较大深度迫使沟道电流的大多数载流子随着它们在氧化物区域116下面并朝向漏极区域104移动时加速。大多数载流子的加速有助于减小实例晶体管100的比电阻。
氧化物区域116可用在其它类型的晶体管中,例如双扩散金属氧化物半导体(DMOS)晶体管以及其它类型的横向或垂直晶体管。尽管在图1中未展示,但是其它半导体装置可在半导体衬底102中形成且耦合到实例晶体管100以实现各种电路。在其它半导体装置与实例晶体管100集成的一些实施例中,在实例晶体管100周围形成硅沟槽隔离(STI)区域以提供与其它半导体装置的电隔离。
图2展示根据实施例的在工艺流程的部分期间半导体衬底102及形成的数个层的横截面图(未按比例绘制)。在半导体衬底102上形成牺牲电介质层204。在硅技术中,牺牲电介质层204通常包含二氧化硅,且将被称为牺牲氧化物层204。在牺牲氧化物层204上沉积阻挡层206,通常为氮化硅。在阻挡层206上沉积底部抗反射涂层(BARC)208,且在BARC 208上沉积光致抗蚀剂层210。
光致抗蚀剂层210根据由掩模(未展示)定义的照射图案暴露于辐射。照射在光致抗蚀剂层210上的图案定义用于生长图1的氧化物区域116的开口。在图2的实例中,箭头(例如箭头212)图示地表示辐射。在一些实施例中,辐射可在深紫外线(DUV)区域中,举例来说,例如波长为248nm,或对于氟化氩准分子激光源,波长为193nm。随着工艺技术节点向更小的尺寸移动,实施例可利用其它类型的照射源及掩模,例如与反射掩模(未展示)一起使用的极紫外线(EUC)激光器。
图2未展示在半导体衬底102内及其上形成的所有特征。例如,可形成掩埋层及STI区域,以电隔离在半导体衬底102内及其上形成的各种装置。
图3展示根据实施例的在执行蚀刻以提供开口302之后,具有图2的层的硅衬底102的横截面图(未按比例绘制)。蚀刻可包括等离子体反应离子蚀刻(RIE)。等离子体RIE可在氧气(O2)、载气(例如氩气)或氟碳化合物的气体混合物中执行,所述氟碳化合物包含碳(C)、氢(H)及氟(F),具有化学计量CxHyFz,其中x=1或2;y=0、1、2、3或4;及z=1、2、3或4。
图4展示根据实施例的具有图3的层的硅衬底102的横截面图(未按比例绘制),其中氧化物区域116已经生长。对于一些实施例,氧化物区域116可具有至少400埃的厚度,例如在400埃到4000埃的范围内。半导体衬底102暴露于环境氧化剂以生长氧化物区域116。对于一些实施例,环境氧化是在使用氧气及/或蒸汽的热炉氧化工艺中进行的。对于一些实施例,半导体衬底102在高于900℃的温度下(例如在950℃至1000℃的范围内)暴露于氧气及/或蒸汽。
由于阻挡层206下方的横向氧化,阻挡层206的厚度影响氧化物区域116的“鸟嘴”(有时也称为“鸟喙”)形状的形成。阻挡层206的厚度可具有300埃到1000埃的厚度。在一些实施例中,阻挡层206可为约950埃厚。
在形成氧化物区域116之后,移除图4所说明的半导体衬底102上方的各个层(除氧化物区域116之外),然后是制造晶体管的额外工艺步骤,例如图1的实例晶体管100。例如,可将掺杂剂植入以形成轻掺杂n型区域110、漏极区域104及源极区域106。在生长栅极氧化物层112之前移除牺牲氧化物层204,且栅极114在栅极氧化物层112上方形成。
图5展示实例工艺流程500。在步骤501中,实例工艺流程500包括形成一或多个STI区域;在步骤502中,在半导体衬底(例如,半导体衬底102)上形成第一电介质层(例如,牺牲氧化物层204);在步骤504中,在第一电介质层上沉积阻挡层206(例如,氮化硅层);在步骤506中,在阻挡层上沉积抗反射涂层(例如,BARC 208);在步骤508中,沉积光致抗蚀剂层(例如,光致抗蚀剂层210);在步骤510中,使光致抗蚀剂层中的图案暴露于辐射;在步骤512中,根据图案蚀刻光致抗蚀剂层以在光致抗蚀剂层中提供开口;在步骤514中,蚀刻光致抗蚀剂层中的开口下方的抗反射涂层的一部分;在步骤516中,蚀刻开口下方的阻挡层的一部分以暴露第一电介质层的一部分;在步骤518中,在蚀刻开口下方的阻挡层的所述部分之后提供环境氧化剂;在步骤520中,在提供环境氧化剂之后移除阻挡层;在步骤522中,在移除阻挡层之后将掺杂剂植入到半导体衬底中(例如,用于形成漏极区域104或源极区域106);在步骤524中,在将掺杂剂植入到半导体衬底中之后移除第一电介质层;及在步骤526中,在移除第一电介质层之后形成第二电介质层(例如,栅极氧化物层112)。
根据实施例的制造晶体管的工艺步骤(例如,工艺流程500)可并入到标准工艺流程中,例如,标准BiCMOS工艺或线性BiCMOS(LBC)工艺。可在实施例中的工艺步骤(例如关于图5描述的工艺步骤)之前及之后执行额外工艺步骤。例如,可在工艺流程500之前执行将掺杂剂植入到半导体衬底102中以形成掩埋区域。作为另一实例,可在工艺流程500之前在半导体衬底102上生长外延层。
当在晶圆上制造多个装置时,可重复图5所说明的一些或全部步骤。例如,可重复步骤526(及与步骤526相关的步骤)以制造对于其相应的栅极氧化物层具有不同厚度的多个晶体管。作为具体实例,在步骤526的迭代中形成的电介质层可具有约40埃的厚度,使得一或多个晶体管被制造成具有约40埃的栅极氧化物层。在步骤526的另一迭代中,电介质层可具有约100埃的厚度,使得一或多个晶体管被制造成具有约100埃的栅极氧化物层,适于较高的操作电压。
图6展示两个实例晶体管的横截面图(未按比例绘制)。图6展示在其中形成实例晶体管100的半导体衬底602,但其中未展示高掺杂p型区域118(主体接触)。在半导体衬底602中形成实例晶体管600(其主体接触未展示)。STI区域601将实例晶体管100与实例晶体管600隔离。
实例晶体管600包含漏极区域604及源极区域606。在图6的实例中,实例晶体管600是n型DEMOS晶体管,其中漏极区域604及源极区域606每一者是高掺杂n型区域。源极区域606在轻掺杂p型阱608内形成,且漏极区域604通过轻掺杂n型区域610延伸。
在半导体衬底602上形成栅极氧化物层(电介质层)612。在栅极氧化物层612上方形成栅极614。氧化物区域616生长在半导体衬底602上且进入半导体衬底602中。氧化物区域616邻近于漏极区域604且在栅极614下方,且氧化物区域616比栅极氧化物层612厚。栅极氧化物层612比栅极氧化物层112厚,使得实例晶体管600能承受比实例晶体管100更高的操作电压。
在权利要求书的范围内,在所描述的实施例中修改是可行的,且其它实施例是可行的。
Claims (20)
1.一种制造晶体管的方法,所述方法包含:
在半导体衬底上形成第一电介质层;
在所述第一电介质层上沉积阻挡层;
在所述阻挡层上沉积抗反射涂层;
沉积光致抗蚀剂层;
使所述光致抗蚀剂层中的图案暴露于辐射;
根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;
蚀刻所述光致抗蚀剂层中的所述开口下方的所述抗反射涂层的一部分;
蚀刻所述开口下方的所述阻挡层的一部分以暴露所述第一电介质层的一部分;
在蚀刻所述开口下方的所述阻挡层的所述部分之后提供环境氧化剂,以生长氧化物区域;
在提供所述环境氧化剂之后移除所述阻挡层;
在移除所述阻挡层之后将掺杂剂植入到所述半导体衬底中;
在将所述掺杂剂植入到所述半导体衬底之后移除所述第一电介质层;及
在移除所述第一电介质层之后形成第二电介质层,其中所述氧化物区域生长为比所述第二电介质层厚。
2.根据权利要求1所述的方法,其进一步包含:
形成浅沟槽隔离STI区域;及
形成第三电介质层,其中所述第三电介质层比所述第二电介质层厚。
3.根据权利要求1所述的方法,其进一步包含:
在所述第二电介质层上沉积第二光致抗蚀剂层;
使所述第二光致抗蚀剂层中的第二图案暴露于辐射;
根据所述第二图案蚀刻所述第二光致抗蚀剂层以在所述第二光致抗蚀剂层中提供开口;及
通过所述第二光致抗蚀剂层中的所述开口在所述第二电介质层上沉积导电材料。
4.根据权利要求3所述的方法,其进一步包含:
在所述半导体衬底上形成所述第一电介质层之前,在所述半导体衬底上生长外延层。
5.根据权利要求4所述的方法,其进一步包含:
在生长所述外延层之前,将掺杂剂植入到所述半导体中以形成n型掩埋层。
6.根据权利要求5所述的方法,其中将掺杂剂植入到所述半导体中形成所述半导体衬底中的漏极区域。
7.根据权利要求1所述的方法,其中提供所述环境氧化剂包含使所述半导体衬底在高于900℃的温度下暴露于所述环境氧化剂。
8.根据权利要求1所述的方法,其中所述氧化剂包含氧气或蒸汽。
9.根据权利要求1所述的方法,其中所述第一及第二电介质层每一者包含二氧化硅。
10.根据权利要求1所述的方法,其中提供所述环境氧化剂包含使所述氧化物区域生长到所述半导体衬底中及在所述半导体衬底上,达至少400埃的厚度。
11.根据权利要求1所述的方法,其中所述阻挡层具有在300埃到1000埃之间的厚度。
12.根据权利要求1所述的方法,其中所述阻挡层包含氮化硅。
13.根据权利要求1所述的方法,其中蚀刻所述抗反射涂层的所述部分及所述开口下方的所述阻挡层包含等离子体反应离子蚀刻RIE。
14.根据权利要求13所述的方法,其中所述等离子体RIE包括使用氧气O2、载气或氟碳化合物的气体混合物,所述氟碳化合物包含碳C、氢H及氟F,具有化学计量CxHyFz,其中x=1或2;y=0、1、2、3或4;及z=1、2、3或4。
15.根据权利要求14所述的方法,其中所述气体包含氩气及氧气。
16.根据权利要求15所述的方法,其中所述阻挡层包含具有在300埃至1000埃之间的厚度的氮化硅。
17.根据权利要求1所述的方法,其中提供所述环境氧化剂包含使所述氧化物区域生长到所述半导体衬底中及在所述半导体衬底上,所述氧化物区域具有至少400埃的厚度。
18.一种制造晶体管的方法,所述方法包含:
在半导体衬底上形成牺牲氧化物层;
在所述牺牲氧化物层上沉积氮化硅层;
在所述氮化硅层上沉积抗反射涂层;
沉积光致抗蚀剂层;
使所述光致抗蚀剂层中的图案暴露于辐射;
根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;
蚀刻所述开口下方的所述抗反射涂层的一部分;
蚀刻所述开口下方的所述氮化硅层的一部分以暴露所述牺牲氧化物层的一部分;及
在所述牺牲氧化物层的所述暴露部分上生长氧化物区域;
在生长所述氧化区域之后移除所述氮化硅层;
在移除所述氮化硅层之后,将掺杂剂植入到所述半导体衬底中;
在将掺杂剂植入到所述半导体衬底之后移除所述牺牲氧化物层;及
在移除所述牺牲氧化物层之后在所述半导体衬底上形成栅极氧化物层,其中所述氧化物区域生长成厚度大于所述栅极氧化物层的厚度。
19.根据权利要求18所述的方法,其中在所述牺牲氧化物层的所述暴露部分上生长所述氧化物区域包含使所述氧化物区域生长到至少400埃的厚度。
20.一种制造晶体管的方法,所述方法包含:
在半导体衬底上形成牺牲氧化物层;
在所述牺牲氧化物层上沉积氮化硅层;
沉积光致抗蚀剂层;
使所述光致抗蚀剂层中的图案暴露于辐射;
根据所述图案蚀刻所述光致抗蚀剂层以在所述光致抗蚀剂层中提供开口;
蚀刻所述开口下方的所述氮化硅层的一部分以暴露所述牺牲氧化物层的一部分;
在所述牺牲氧化物层的所述暴露部分上生长至少400埃厚的氧化物区域;
在生长所述氧化物区域之后移除所述氮化硅层;
在移除所述氮化硅层之后,将掺杂剂植入到所述半导体衬底中,以在所述半导体衬底中形成漏极区域;
在将掺杂剂植入到所述半导体衬底中之后移除所述牺牲氧化物层;及
在移除所述牺牲氧化物层之后在所述半导体衬底上形成栅极氧化物层,所述栅极氧化物层具有小于400埃的厚度。
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2018
- 2018-04-03 US US15/944,550 patent/US10566200B2/en active Active
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2019
- 2019-04-03 CN CN201980029913.7A patent/CN112074932A/zh active Pending
- 2019-04-03 WO PCT/US2019/025599 patent/WO2019195435A1/en unknown
- 2019-04-03 JP JP2020554400A patent/JP2021521629A/ja active Pending
- 2019-04-03 EP EP19781451.0A patent/EP3776637A4/en not_active Withdrawn
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US20040238913A1 (en) * | 2002-05-09 | 2004-12-02 | Kwon Tae-Hun | Reduced surface field technique for semiconductor devices |
JP2004200359A (ja) * | 2002-12-18 | 2004-07-15 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
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WO2019195435A1 (en) | 2019-10-10 |
US10566200B2 (en) | 2020-02-18 |
JP2021521629A (ja) | 2021-08-26 |
EP3776637A4 (en) | 2021-05-05 |
US20190304786A1 (en) | 2019-10-03 |
EP3776637A1 (en) | 2021-02-17 |
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