KR100817417B1 - 고전압 씨모스 소자 및 그 제조 방법 - Google Patents
고전압 씨모스 소자 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100817417B1 KR100817417B1 KR1020060134236A KR20060134236A KR100817417B1 KR 100817417 B1 KR100817417 B1 KR 100817417B1 KR 1020060134236 A KR1020060134236 A KR 1020060134236A KR 20060134236 A KR20060134236 A KR 20060134236A KR 100817417 B1 KR100817417 B1 KR 100817417B1
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- Prior art keywords
- high voltage
- semiconductor substrate
- forming
- deep well
- oxide layer
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (7)
- 반도체 기판 위에 제1 산화막을 형성하는 단계;상기 제1 산화막을 식각하여 제1 산화막 패턴을 형성하는 단계;상기 식각에 의해 노출된 반도체 기판에 제2 산화막 패턴을 형성하는 단계;상기 제1 산화막 패턴을 마스크로 삼아 불순물 이온을 주입하여 고전압 딥웰을 형성하고, 상기 제1 산화막 패턴을 제거하는 단계;상기 제2 산화막 패턴을 제거하여 상기 고전압 딥웰의 상부에 단차를 형성하는 단계;상기 반도체 기판에 소자 분리 영역을 형성하는 단계; 및,상기 반도체 기판에 절연막을 증착한 후, 식각하여 상기 단차의 측면에 스페이서를 형성하는 단계를 포함하는 고전압 씨모스 소자 제조 방법.
- 제 1 항에 있어서,상기 제1 산화막을 3000 내지 7000Å으로 형성하는 고전압 씨모스 소자 제조 방법.
- 제 1 항에 있어서,상기 제1 산화막을 5000Å으로 형성하는 고전압 씨모스 소자 제조 방법.
- 제 1 항에 있어서,상기 제2 산화막 패턴을 600 내지 1000Å으로 형성하는 고전압 씨모스 소자 제조 방법.
- 제 1 항에 있어서,상기 제2 산화막 패턴을 800Å으로 형성하는 고전압 씨모스 소자 제조 방법.
- 반도체 기판, 및 상기 반도체 기판에 형성된 고전압 딥웰;상기 고전압 딥웰의 내부에 형성된 로직 웰;상기 고전압 딥웰의 표면에 형성된 소스 및 드레인 영역들;상기 고전압 딥웰 표면의 에지 부분에 형성된 단차; 및,상기 단차의 측면에 형성된 절연막으로 이루어진 스페이서를 포함하고,상기 소스 및 드레인 영역들 중에서 어느 하나의 영역은 상기 고전압 딥웰의 내부에 형성되고, 다른 영역은 상기 로직 웰의 내부에 형성되는 것을 특징으로 하는 고전압 씨모스 소자.
- 제 6 항에 있어서,상기 절연막은 질화막인 고전압 씨모스 소자.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060134236A KR100817417B1 (ko) | 2006-12-26 | 2006-12-26 | 고전압 씨모스 소자 및 그 제조 방법 |
US11/842,810 US7524721B2 (en) | 2006-12-26 | 2007-08-21 | High voltage CMOS device and method of fabricating the same |
DE102007040869A DE102007040869B4 (de) | 2006-12-26 | 2007-08-29 | Verfahren zur Herstellung eines Hochvolt-CMOS-Bauelementes und Bauelement |
CNB2007101537038A CN100568488C (zh) | 2006-12-26 | 2007-09-14 | 高压cmos器件及其制造方法 |
JP2007264359A JP4836914B2 (ja) | 2006-12-26 | 2007-10-10 | 高電圧シーモス素子及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060134236A KR100817417B1 (ko) | 2006-12-26 | 2006-12-26 | 고전압 씨모스 소자 및 그 제조 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR100817417B1 true KR100817417B1 (ko) | 2008-03-27 |
Family
ID=39411920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020060134236A KR100817417B1 (ko) | 2006-12-26 | 2006-12-26 | 고전압 씨모스 소자 및 그 제조 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7524721B2 (ko) |
JP (1) | JP4836914B2 (ko) |
KR (1) | KR100817417B1 (ko) |
CN (1) | CN100568488C (ko) |
DE (1) | DE102007040869B4 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105819395B (zh) * | 2015-01-09 | 2017-09-05 | 中国科学院微电子研究所 | 半导体器件制造方法 |
CN106206725B (zh) * | 2015-05-08 | 2019-04-30 | 北大方正集团有限公司 | 射频水平双扩散金属氧化物半导体器件及制作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980048775A (ko) * | 1996-12-18 | 1998-09-15 | 김광호 | 반도체 메모리 장치의 트윈 우물영역 제조 방법 |
KR0180134B1 (ko) * | 1995-03-17 | 1999-04-15 | 김주용 | 트윈 웰 형성 방법 |
KR20040057833A (ko) * | 2002-12-26 | 2004-07-02 | 주식회사 하이닉스반도체 | 고전압 트랜지스터를 구비한 반도체 소자의 제조방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR940003026A (ko) * | 1992-07-13 | 1994-02-19 | 김광호 | 트리플웰을 이용한 반도체장치 |
EP0716443B1 (en) * | 1994-12-08 | 2000-10-11 | AT&T Corp. | Fabrication of integrated circuit having twin tubs |
JP2000133701A (ja) * | 1998-10-23 | 2000-05-12 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH11354523A (ja) * | 1999-05-21 | 1999-12-24 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US6350641B1 (en) * | 2000-05-17 | 2002-02-26 | United Microelectronics Corp. | Method of increasing the depth of lightly doping in a high voltage device |
JP2003257883A (ja) * | 2002-03-06 | 2003-09-12 | Seiko Epson Corp | 半導体装置の製造方法 |
US7902029B2 (en) * | 2002-08-12 | 2011-03-08 | Acorn Technologies, Inc. | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor |
JP2004172275A (ja) * | 2002-11-19 | 2004-06-17 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2004172274A (ja) * | 2002-11-19 | 2004-06-17 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
-
2006
- 2006-12-26 KR KR1020060134236A patent/KR100817417B1/ko active IP Right Grant
-
2007
- 2007-08-21 US US11/842,810 patent/US7524721B2/en active Active
- 2007-08-29 DE DE102007040869A patent/DE102007040869B4/de not_active Expired - Fee Related
- 2007-09-14 CN CNB2007101537038A patent/CN100568488C/zh not_active Expired - Fee Related
- 2007-10-10 JP JP2007264359A patent/JP4836914B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0180134B1 (ko) * | 1995-03-17 | 1999-04-15 | 김주용 | 트윈 웰 형성 방법 |
KR19980048775A (ko) * | 1996-12-18 | 1998-09-15 | 김광호 | 반도체 메모리 장치의 트윈 우물영역 제조 방법 |
KR20040057833A (ko) * | 2002-12-26 | 2004-07-02 | 주식회사 하이닉스반도체 | 고전압 트랜지스터를 구비한 반도체 소자의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
CN100568488C (zh) | 2009-12-09 |
CN101211852A (zh) | 2008-07-02 |
US7524721B2 (en) | 2009-04-28 |
JP4836914B2 (ja) | 2011-12-14 |
US20080150034A1 (en) | 2008-06-26 |
DE102007040869A1 (de) | 2008-07-10 |
JP2008166704A (ja) | 2008-07-17 |
DE102007040869B4 (de) | 2009-08-06 |
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