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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/65—Lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0144—Manufacturing their gate insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/836—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising EDMOS

Definitions

• transistors should have a relatively low specific resistance.
• field-effect-transistors such as drain-extended metal-oxide-semiconductor (DEMOS) transistors
• DEMOS drain-extended metal-oxide-semiconductor
• a method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the anti -reflective coating below the opening in the photoresist layer; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent after etching the portion of the barrier layer below the opening to grow an oxide region; removing the barrier layer after providing the ambient oxidizing agent; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer,
• a method to fabricate a transistor comprises: forming a sacrificial oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the sacrificial oxide layer; depositing an anti -reflective coating on the silicon nitride layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the anti-reflective coating below the opening; etching a portion of the silicon nitride layer below the opening to expose a portion of the sacrificial oxide layer; and growing an oxide region on the exposed portion of the sacrificial oxide layer; removing the silicon nitride layer after growing the oxide region; implanting dopants into the semiconductor substrate after removing the silicon nitride layer; removing the sacrificial oxide layer after implanting dopants into the semiconductor
• a method to fabricate a transistor comprises: forming a sacrificial oxide layer on a semiconductor substrate; depositing a silicon nitride layer on the sacrificial oxide layer; depositing a photoresist layer; exposing a pattern in the photoresist layer to radiation; etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; etching a portion of the silicon nitride layer below the opening to expose a portion of the sacrificial oxide layer; growing an oxide region of at least 400 angstroms thick on the exposed portion of the sacrificial oxide layer; removing the silicon nitride layer after growing the oxide region; implanting dopants into the semiconductor substrate after removing the silicon nitride layer to form a drain region in the semiconductor substrate; removing the sacrificial oxide layer after implanting dopants into the semiconductor substrate; and forming a gate oxide layer on the semiconductor substrate after removing the s
• FIG. 1 shows a transistor in various examples.
• FIG. 2 shows a semiconductor substrate with several layers in various examples.
• FIG. 3 shows a silicon substrate after etching in various examples.
• FIG. 4 shows a silicon substrate with an oxide region in various examples.
• FIG. 5 shows a process flow in various examples.
• FIG. 6 shows two transistors in various examples.
• a method to fabricate transistors includes growing a thick oxide below the transistor gate, where the process steps can be incorporated into a standard bipolar complementary-metal-oxide-semiconductor (BiCMOS) process flow.
• BiCMOS bipolar complementary-metal-oxide-semiconductor
• FIG. 1 shows a cross-sectional view of an example transistor 100, not drawn to scale.
• the example transistor 100 is a DEMOS transistor.
• a drain region 104 and a source region 106 are formed in a semiconductor substrate 102.
• the semiconductor substrate 102 is a silicon crystal
• the example transistor 100 is an n-type DEMOS transistor, where the drain region 104 and the source region 106 are each highly doped n- type regions.
• the source region 106 is formed within a lightly doped p-type well 108, and the drain region 104 is extended by way of the lightly doped n-type region 110.
• a dielectric layer 112 is formed on the semiconductor substrate 102.
• the dielectric layer 112 is usually silicon dioxide, and the dielectric layer 112 is referred to as a gate oxide layer 112.
• a gate 114 is formed over the gate oxide layer 112.
• the gate 114 may comprise polysilicon.
• An oxide region 116 is grown on and into the semiconductor substrate 102.
• the oxide region 116 is adjacent to the drain region 104 and is below the gate 114, and the oxide region 116 is thicker than the dielectric layer 112.
• the oxide region 116 may comprise silicon dioxide.
• the presence of the oxide region 116 provides a lift-up to the gate 114.
• a highly doped p-type region 118 serves as a body contact for the example transistor 100.
• a channel current of majority carriers (e.g., electrons for an n-type channel) flows from the source region 106 to the drain region 104.
• the presence of the oxide region 116 affects the path of the channel current.
• the relatively large depth of the oxide region 116 into the channel forces the majority carriers of the channel current to accelerate as they move underneath the oxide region 116 and toward the drain region 104. The acceleration of the majority carriers helps to reduce the specific resistance of the example transistor 100.
• the oxide region 116 may be employed in other types of transistors, such as a double-diffusion metal-oxide-semiconductor (DMOS) transistor, as well as other types of lateral or vertical transistors.
• DMOS metal-oxide-semiconductor
• other semiconductor devices may be formed in the semiconductor substrate 102 and coupled to the example transistor 100 to realize various circuits.
• a silicon trench isolation (STI) region is formed around the example transistor 100 to provide electrical isolation from other semiconductor devices.
• FIG. 2 shows a cross-sectional view (not drawn to scale) of the semiconductor substrate 102 and several layers formed during part of a process flow according to embodiments.
• a sacrificial dielectric layer 204 is formed over the semiconductor substrate 102.
• the sacrificial dielectric layer 204 typically comprises silicon dioxide, and will be referred to as a sacrificial oxide layer 204.
• a barrier layer 206 typically silicon nitride, is deposited on the sacrificial oxide layer 204.
• a bottom antireflective coating (BARC) 208 is deposited on the barrier layer 206, and a photoresist layer 210 is deposited on the BARC 208.
• BARC bottom antireflective coating
• the photoresist layer 210 is exposed to radiation according to an illumination pattern defined by a mask (not shown).
• the pattern illuminated on the photoresist layer 210 defines an opening for growing the oxide region 116 of FIG. 1.
• arrows such as an arrow 212, pictorially represent the radiation.
• the radiation may be in the deep ultraviolet (DUV) region, such as, for example, a wavelength of 248 nm, or a wavelength of 193 nm for an argon fluoride excimer laser source.
• DUV deep ultraviolet
• EUV extreme ultraviolet
• FIG. 2 does not show all features formed within and on the semiconductor substrate 102.
• buried layers and STI regions may be formed to electrically isolate various devices formed within and on the semiconductor substrate 102.
• FIG. 3 shows a cross-sectional view (not drawn to scale) of the silicon substrate 102, with the layers of FIG. 2, after etching is performed to provide an opening 302, according to embodiments.
• the etching may include plasma reactive-ion etching (RIE).
• FIG. 4 shows a cross-sectional view (not drawn to scale) of the silicon substrate 102, with the layers of FIG. 3, where the oxide region 116 has been grown, according to embodiments.
• the oxide region 116 may have a thickness of at least 400 angstroms, for example in the range of 400 angstroms to 4000 angstroms.
• the semiconductor substrate 102 is exposed to an ambient oxidizing agent to grow the oxide region 116.
• the ambient oxidizing is performed in a thermal furnace oxidation process using oxygen and/or steam.
• the semiconductor substrate 102 is exposed to oxygen and/or steam at a temperature above 900°C, for example in the range of 950°C to l000°C.
• the thickness of the barrier layer 206 affects formation of the“bird’s beak” (also sometimes referred to as a“birds beak”) shape of the oxide region 116 because of lateral oxidation under the barrier layer 206.
• the thickness of the barrier layer 206 may have a thickness from 300 angstroms to 1000 angstroms. In some embodiments, the barrier layer 206 may be about 950 angstroms thick.
• the various layers (excluding the oxide region 116) above the semiconductor substrate 102 illustrated in FIG. 4 are removed, followed by additional process steps to fabricate a transistor, such the example transistor 100 of FIG. 1.
• dopants can be implanted to form the lightly doped n-type region 110, the drain region 104, and the source region 106.
• the sacrificial oxide layer 204 is removed before growing the gate oxide layer 112, and the gate 114 is formed over the gate oxide layer 112.
• FIG. 5 shows an example process flow 500.
• the example process flow 500 includes, in step 501, formation of one or more STI regions; in step 502, forming a first dielectric layer (e.g., the sacrificial oxide layer 204) on a semiconductor substrate (e.g., the semiconductor substrate 102); in step 504, depositing a barrier layer 206 (e.g., a silicon nitride layer) on the first dielectric layer; in step 506, depositing an anti-reflective coating (e.g., the BARC 208) on the barrier layer; in step 508, depositing a photoresist layer (e.g., the photoresist layer 210); in step 510, exposing a pattern in the photoresist layer to radiation; in step 512, etching the photoresist layer according to the pattern to provide an opening in the photoresist layer; in step 514, etching a portion of the anti- reflective coating below the opening in the photoresist layer; in step 516,
• the process steps in fabricating a transistor according to embodiments can be incorporated into a standard process flow, for example, a standard BiCMOS process, or a linear BiCMOS (LBC) process. Additional process steps may be performed before and after the process steps in an embodiment, such as the process steps described with respect to FIG. 5. For example, implanting dopants into the semiconductor substrate 102 to form buried regions may be performed before the process flow 500. As another example, an epitaxial layer may be grown on the semiconductor substrate 102 before the process flow 500.
• a standard BiCMOS process for example, a standard BiCMOS process, or a linear BiCMOS (LBC) process. Additional process steps may be performed before and after the process steps in an embodiment, such as the process steps described with respect to FIG. 5.
• implanting dopants into the semiconductor substrate 102 to form buried regions may be performed before the process flow 500.
• an epitaxial layer may be grown on the semiconductor substrate 102 before the process flow 500.
• step 526 may be repeated to fabricate multiple transistors having different thicknesses for their respective gate oxide layers.
• the dielectric layer formed in an iteration of step 526 may have a thickness of about 40 angstroms, so that one or more transistors are fabricated having a gate oxide layer of about 40 angstroms.
• the dielectric layer may have a thickness of about 100 angstroms, so that one or more transistors are fabricated having a gate oxide layer of about 100 angstroms, suitable for a higher operating voltage.
• FIG. 6 shows a cross-sectional view (not drawn to scale) of two example transistors.
• FIG. 6 shows a semiconductor substrate 602 in which the example transistor 100 is formed, but where the highly doped p-type region 118 (body contact) is not shown.
• Formed in the semiconductor substrate 602 is an example transistor 600 (with its body contact not shown).
• An STI region 601 isolates the example transistor 100 from the example transistor 600.
• the example transistor 600 comprises a drain region 604 and a source region 606.
• the example transistor 600 is an n-type DEMOS transistor, where the drain region 604 and the source region 606 are each highly doped n-type regions.
• the source region 606 is formed within a lightly doped p-type well 608, and the drain region 604 is extended by way of the lightly doped n-type region 610.
• a gate oxide layer (a dielectric layer) 612 is formed on the semiconductor substrate 602.
• a gate 614 is formed over the gate oxide layer 612.
• An oxide region 616 is grown on and into the semiconductor substrate 602. The oxide region 616 is adjacent to the drain region 604 and is below the gate 614, and the oxide region 616 is thicker than the gate oxide layer 612.
• the gate oxide layer 612 is thicker than the gate oxide layer 112, so that the example transistor 600 can withstand a higher operating voltage than the example transistor 100.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2018
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