CN112074932A - 制造晶体管的方法 - Google Patents
制造晶体管的方法 Download PDFInfo
- Publication number
- CN112074932A CN112074932A CN201980029913.7A CN201980029913A CN112074932A CN 112074932 A CN112074932 A CN 112074932A CN 201980029913 A CN201980029913 A CN 201980029913A CN 112074932 A CN112074932 A CN 112074932A
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- China
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- layer
- semiconductor substrate
- etching
- oxide
- dielectric layer
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/836—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising EDMOS
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/944,550 US10566200B2 (en) | 2018-04-03 | 2018-04-03 | Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings |
| US15/944,550 | 2018-04-03 | ||
| PCT/US2019/025599 WO2019195435A1 (en) | 2018-04-03 | 2019-04-03 | Method of fabricating transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112074932A true CN112074932A (zh) | 2020-12-11 |
Family
ID=68055429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980029913.7A Pending CN112074932A (zh) | 2018-04-03 | 2019-04-03 | 制造晶体管的方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10566200B2 (https=) |
| EP (1) | EP3776637A4 (https=) |
| JP (1) | JP2021521629A (https=) |
| CN (1) | CN112074932A (https=) |
| WO (1) | WO2019195435A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11227926B2 (en) * | 2020-06-01 | 2022-01-18 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
| CN116417404B (zh) * | 2021-12-30 | 2026-04-14 | 无锡华润上华科技有限公司 | 双栅结构、场氧结构及半导体器件的制造方法 |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196578A (ja) * | 1999-10-29 | 2001-07-19 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
| JP2004200359A (ja) * | 2002-12-18 | 2004-07-15 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
| US20040238913A1 (en) * | 2002-05-09 | 2004-12-02 | Kwon Tae-Hun | Reduced surface field technique for semiconductor devices |
| CN1661779A (zh) * | 2004-01-29 | 2005-08-31 | 罗姆及海斯电子材料有限公司 | T栅的形成 |
| CN101218675A (zh) * | 2005-07-07 | 2008-07-09 | 密克罗奇普技术公司 | 具有不同厚度栅极氧化物的esd结构 |
| US20100270614A1 (en) * | 2009-04-22 | 2010-10-28 | Stmicroelectronics S.R.L. | Process for manufacturing devices for power applications in integrated circuits |
| US20130082331A1 (en) * | 2011-10-04 | 2013-04-04 | Fujitsu Semiconductor Limited | Semiconductor device and semiconductor device manufacturing method |
| CN106471615A (zh) * | 2015-03-09 | 2017-03-01 | 赛普拉斯半导体公司 | Ono堆叠形成方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4040168A (en) | 1975-11-24 | 1977-08-09 | Rca Corporation | Fabrication method for a dual gate field-effect transistor |
| US5512495A (en) * | 1994-04-08 | 1996-04-30 | Texas Instruments Incorporated | Method of manufacturing extended drain resurf lateral DMOS devices |
| KR100225411B1 (ko) * | 1997-03-24 | 1999-10-15 | 김덕중 | LDMOS(a lateral double-diffused MOS) 트랜지스터 소자 및 그의 제조 방법 |
| JPH1167904A (ja) * | 1997-08-15 | 1999-03-09 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US6121133A (en) * | 1997-08-22 | 2000-09-19 | Micron Technology, Inc. | Isolation using an antireflective coating |
| JP2000353804A (ja) * | 1999-06-11 | 2000-12-19 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP2005123314A (ja) * | 2003-10-15 | 2005-05-12 | Semiconductor Leading Edge Technologies Inc | パターン形成方法 |
| DE102004031741B4 (de) | 2004-06-30 | 2010-04-01 | Qimonda Ag | Verfahren zur Herstellung einer Kontaktanordnung für Feldeffekttransistorstrukturen mit Gateelektroden mit einer Metalllage und Verwendung des Verfahrens zur Herstellung von Feldeffekttransistoranordnungen in einem Zellenfeld |
| KR20060070334A (ko) | 2004-12-20 | 2006-06-23 | 삼성전자주식회사 | 박막 트랜지스터 표시판의 제조 방법 |
| US20070018199A1 (en) | 2005-07-20 | 2007-01-25 | Cree, Inc. | Nitride-based transistors and fabrication methods with an etch stop layer |
| JP5272410B2 (ja) * | 2008-01-11 | 2013-08-28 | 富士電機株式会社 | 半導体装置およびその製造方法 |
| JP5887233B2 (ja) * | 2012-09-10 | 2016-03-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2014192361A (ja) * | 2013-03-27 | 2014-10-06 | Sharp Corp | 半導体装置およびその製造方法 |
| US9583612B1 (en) * | 2016-01-21 | 2017-02-28 | Texas Instruments Incorporated | Drift region implant self-aligned to field relief oxide with sidewall dielectric |
-
2018
- 2018-04-03 US US15/944,550 patent/US10566200B2/en active Active
-
2019
- 2019-04-03 JP JP2020554400A patent/JP2021521629A/ja active Pending
- 2019-04-03 EP EP19781451.0A patent/EP3776637A4/en not_active Withdrawn
- 2019-04-03 CN CN201980029913.7A patent/CN112074932A/zh active Pending
- 2019-04-03 WO PCT/US2019/025599 patent/WO2019195435A1/en not_active Ceased
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196578A (ja) * | 1999-10-29 | 2001-07-19 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
| US20040238913A1 (en) * | 2002-05-09 | 2004-12-02 | Kwon Tae-Hun | Reduced surface field technique for semiconductor devices |
| JP2004200359A (ja) * | 2002-12-18 | 2004-07-15 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
| CN1661779A (zh) * | 2004-01-29 | 2005-08-31 | 罗姆及海斯电子材料有限公司 | T栅的形成 |
| CN101218675A (zh) * | 2005-07-07 | 2008-07-09 | 密克罗奇普技术公司 | 具有不同厚度栅极氧化物的esd结构 |
| US20100270614A1 (en) * | 2009-04-22 | 2010-10-28 | Stmicroelectronics S.R.L. | Process for manufacturing devices for power applications in integrated circuits |
| US20130082331A1 (en) * | 2011-10-04 | 2013-04-04 | Fujitsu Semiconductor Limited | Semiconductor device and semiconductor device manufacturing method |
| CN106471615A (zh) * | 2015-03-09 | 2017-03-01 | 赛普拉斯半导体公司 | Ono堆叠形成方法 |
Non-Patent Citations (1)
| Title |
|---|
| 潘桂忠: "MOS集成电路工艺与制造技术", 30 June 2012, 上海科学技术出版社, pages: 27 - 29 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2021521629A (ja) | 2021-08-26 |
| WO2019195435A1 (en) | 2019-10-10 |
| EP3776637A1 (en) | 2021-02-17 |
| US20190304786A1 (en) | 2019-10-03 |
| EP3776637A4 (en) | 2021-05-05 |
| US10566200B2 (en) | 2020-02-18 |
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