JP2020537822A - チップパッケージ構造及びチップパッケージ方法 - Google Patents
チップパッケージ構造及びチップパッケージ方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 216
- 238000001746 injection moulding Methods 0.000 claims abstract description 121
- 239000012778 molding material Substances 0.000 claims abstract description 120
- 238000004806 packaging method and process Methods 0.000 claims abstract description 22
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 7
- 239000007924 injection Substances 0.000 claims abstract description 7
- 238000005520 cutting process Methods 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 5
- 206010040844 Skin exfoliation Diseases 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000006870 function Effects 0.000 description 6
- 238000000926 separation method Methods 0.000 description 5
- 230000003190 augmentative effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- CMLFRMDBDNHMRA-UHFFFAOYSA-N 2h-1,2-benzoxazine Chemical compound C1=CC=C2C=CNOC2=C1 CMLFRMDBDNHMRA-UHFFFAOYSA-N 0.000 description 1
- 241000282376 Panthera tigris Species 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 238000004512 die casting Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
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- H—ELECTRICITY
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
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- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
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Abstract
Description
Claims (13)
- チップパッケージ構造であって、
前記チップパッケージ構造は、ダイと、前記ダイの周囲に配置されたパッケージ基板とを備え、
はんだ接合が、前記ダイの第1の表面上に配置され、第2の表面以外の前記ダイの残りの表面が、射出成形材料によって覆われ、少なくとも1つの前記パッケージ基板の一組の対向側面が前記射出成形材料に埋め込まれ、前記一組の対向側面と前記射出成形材料との間の接触領域は、前記一組の対向側面の表面領域の半分より多くを占め、前記第2の表面は、前記ダイの、前記第1の表面に対向する表面である、
チップパッケージ構造。 - 前記パッケージ基板は、第1の一組の対向側面及び第2の一組の対向側面を有し、前記第1の一組の対向側面の長さは、前記第2の一組の対向側面の長さより長く、
前記第2の一組の対向側面の少なくとも3つの表面が前記射出成形材料と接触するように、前記第2の一組の対向側面が前記射出成形材料に埋め込まれる、
請求項1に記載のチップパッケージ構造。 - 前記第1の一組の対向側面の少なくとも3つの表面が前記射出成形材料と接触するように、前記第1の一組の対向側面が前記射出成形材料に埋め込まれる、請求項2に記載のチップパッケージ構造。
- ターゲット方向における前記第1の一組の対向側面の高さは、前記ターゲット方向における前記第2の一組の対向側面の高さより高く、前記第1の一組の対向側面の第1のターゲット表面は、前記ダイの前記第2の表面と同一平面であり、
前記ターゲット方向は、前記ダイの前記第2の表面に垂直であり、前記第1のターゲット表面は、前記第1の一組の対向側面の、前記ターゲット方向において前記射出成形材料と接触していない表面である、
請求項2に記載のチップパッケージ構造。 - 前記パッケージ基板は、第1の一組の対向側面及び第2の一組の対向側面を有し、前記第1の一組の対向側面の長さは、前記第2の一組の対向側面の長さより長く、
前記第1の一組の対向側面の少なくとも3つの表面が前記射出成形材料と接触するように、前記第1の一組の対向側面が前記射出成形材料に埋め込まれる、
請求項1に記載のチップパッケージ構造。 - ターゲット方向における前記第2の一組の対向側面の高さは、前記ターゲット方向における前記第1の一組の対向側面の高さより高く、前記第2の一組の対向側面の第2のターゲット表面は、前記ダイの前記第2の表面と同一平面であり、
前記ターゲット方向は、前記ダイの前記第2の表面に垂直であり、前記第2のターゲット表面は、前記第2の一組の対向側面の、前記ターゲット方向において前記射出成形材料と接触していない表面である、
請求項5に記載のチップパッケージ構造。 - 前記パッケージ基板と前記射出成形材料との間の接触領域の前記パッケージ基板の表面領域に対する比は、2/3、3/4、又は4/5より大きい、請求項1から6のいずれか一項に記載のチップパッケージ構造。
- 前記パッケージ基板が統合成形処理を用いることによって生成される、請求項1から7のいずれか一項に記載のチップパッケージ構造。
- チップパッケージ方法であって、
前記方法はパッケージ基板を用いることによってダイをパッケージする処理に適用され、前記パッケージ基板は間隔をあけて配置された第1の基板及び第2の基板を含み、ターゲット方向における前記第1の基板の高さは前記ターゲット方向における前記第2の基板の高さより高く、前記ダイを設置するのに用いられる貫通孔が前記第2の基板上に配置され、前記ターゲット方向は前記貫通孔の孔の深さ方向と同一であり、
前記方法は、
前記ダイの第2の表面が前記第1の基板のターゲット表面と同一平面になるように、前記第2の基板の前記貫通孔に前記ダイを設置する段階であって、前記第2の表面は、前記ダイの、はんだ接合が配置される第1の表面に対向する表面であり、前記ターゲット表面は、前記第1の基板の、前記ターゲット方向における前記第2の基板より高い表面である、設置する段階と、
お互いに同一平面である前記第1の基板及び前記ダイの前記第2の表面上にパッケージフィルムを形成する段階と、
射出成形材料が前記パッケージフィルム、前記ダイ、及び前記パッケージ基板の間に形成された隙間を満たすように、前記第2の基板の前記貫通孔に前記射出成形材料を注入する段階と、
前記第1の基板及び前記ダイの前記第2の表面上に形成された前記パッケージフィルムを除去する段階と
を備える、方法。 - 前記第1の基板及び前記ダイの前記第2の表面上に形成された前記パッケージフィルムを前記除去する段階の後、前記方法は、さらに、
前記ダイを含むパッケージされたチップを取得すべく、前記貫通孔の周囲に予め設定された切断境界線に沿って前記パッケージ基板を切断する段階
を備える、請求項9に記載の方法。 - 前記第1の基板及び前記ダイの前記第2の表面上に形成された前記パッケージフィルムを前記除去する段階は、加熱処理及び剥離処理を用いることによって、前記第1の基板及び前記ダイの前記第2の表面上に形成された前記パッケージフィルムを除去する段階を有する、請求項9又は10に記載の方法。
- 前記ターゲット方向における前記貫通孔の投影領域は、前記ターゲット方向における前記ダイの投影領域より大きい、請求項9から11のいずれか一項に記載の方法。
- 前記ダイの前記はんだ接合が前記射出成形材料の外側に露出している、請求項9から12のいずれか一項に記載の方法。
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WO2019075720A1 (zh) | 2019-04-25 |
US20200273770A1 (en) | 2020-08-27 |
KR20200073261A (ko) | 2020-06-23 |
EP3686926A1 (en) | 2020-07-29 |
CN110168717B (zh) | 2021-08-20 |
EP3686926A4 (en) | 2020-08-05 |
JP6943358B2 (ja) | 2021-09-29 |
KR102406916B1 (ko) | 2022-06-08 |
US11309227B2 (en) | 2022-04-19 |
CN110168717A (zh) | 2019-08-23 |
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