JP2012015191A - 半導体パッケージの製造方法及び半導体パッケージ - Google Patents
半導体パッケージの製造方法及び半導体パッケージ Download PDFInfo
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Abstract
【解決手段】複数の半導体チップ12を、互いに離間して整列した状態で支持体24の凹部に配置する。半導体チップ12を支持体上で絶縁樹脂により封止して封止樹脂部30を形成する。封止樹脂部30の上面に再配線パターン32を形成し、その上に外部接続端子を形成する。支持体24の補強部材を残して、支持体24の凹部の底面を封止樹脂部30から除去し、補強部材の外側に沿って封止樹脂部30を切断し個片化して半導体パッケージを製造する。
【選択図】図6
Description
1a 電極
2,30 封止樹脂部
3 再配線パターン
4 はんだバンプ
5 ドライフィルムソルダレジスト
10 シリコンウェハ
12 半導体チップ
12a 電極
14 メタルバンプ
16 ダイアタッチフィルム
20 ダミーウェハ
20a 凹部
22 マスク
24 支持体
30 封止樹脂部
32 再配線パターン
34 ドライフィルムソルダレジスト
36 はんだバンプ
40 半導体パッケージ
Claims (9)
- 複数の半導体チップを、互いに離間して整列した状態で、電極面を上にして支持体上の凹部に搭載し、
前記半導体チップを前記支持体上で絶縁樹脂により封止して封止樹脂部を形成し、
前記封止樹脂部の上面に再配線パターンを形成し、
前記再配線パターン上に外部接続端子を形成し、
前記支持体の補強部材を残して、前記支持体の前記凹部の底面を前記封止樹脂部から除去し、
前記補強部材の外側に沿って前記封止樹脂部を切断し個片化する
ことを特徴とする半導体パッケージの製造方法。 - 請求項1記載の半導体パッケージの製造方法であって、
シリコンウェハの表面に、前記複数の半導体チップを個別に収容する前記凹部を形成することで前記支持体を形成することを特徴とする半導体パッケージの製造方法。 - 請求項2記載の半導体パッケージの製造方法であって、
前記シリコンウェハにマスクを施してからウェットブラスト処理することにより前記凹部を形成することを特徴とする半導体パッケージの製造方法。 - 請求項1乃至3のうちいずれか一項記載の半導体パッケージの製造方法であって、
前記支持体をバックグラインドにより除去することを特徴とする半導体パッケージの製造方法。 - 請求項4記載の半導体パッケージの製造方法であって、
前記半導体チップの背面が露出し、前記支持体の一部が前記半導体チップの周囲に枠状に残っている状態でバックグラインドを止めることを特徴とする半導体パッケージの製造方法。 - 請求項1乃至5のうちいずれか一項記載の半導体パッケージの製造方法であって、
前記複数の半導体チップを前記支持体の前記凹部に搭載してから、前記半導体チップの電極上にメタルバンプを形成することを特徴とする半導体パッケージの製造方法。 - 半導体チップと、
該半導体チップの電極に形成されたバンプの側面を埋めるように形成された封止樹脂部と、
該封止樹脂部の上面に形成された再配線パターンと、
前記封止樹脂部の上面と前記再配線パターン上で、外部接続端子用パッドを除く部分に形成されたソルダレジスト層と、
前記封止樹脂部中に埋め込まれ、前記半導体チップを包囲するように枠形状を有する補強部材と
を有することを特徴とする半導体パッケージ。 - 請求項7記載の半導体パッケージであって、
前記補強部材はシリコンにより形成されたことを特徴とする半導体パッケージ。 - 請求項7記載の半導体パッケージであって、
前記補強部材の下面は、前記封止樹脂部の裏面から露出していることを特徴とする半導体パッケージ。
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JP2010147950A JP5685012B2 (ja) | 2010-06-29 | 2010-06-29 | 半導体パッケージの製造方法 |
US13/170,319 US8779573B2 (en) | 2010-06-29 | 2011-06-28 | Semiconductor package having a silicon reinforcing member embedded in resin |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2016171124A (ja) * | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR20170015260A (ko) * | 2015-07-30 | 2017-02-08 | 셈테크 코포레이션 | 작은 z 치수 패키지를 형성하는 반도체 소자 및 방법 |
US10896827B2 (en) | 2016-06-28 | 2021-01-19 | Zeon Corporation | Support for manufacturing semiconductor packages, use of support for manufacturing semiconductor packages, and method for manufacturing semiconductor packages |
KR20230162620A (ko) | 2021-03-29 | 2023-11-28 | 아지노모토 가부시키가이샤 | 회로 기판의 제조 방법 |
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TWI476841B (zh) * | 2012-03-03 | 2015-03-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9768038B2 (en) * | 2013-12-23 | 2017-09-19 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of making embedded wafer level chip scale packages |
US10811298B2 (en) * | 2018-12-31 | 2020-10-20 | Micron Technology, Inc. | Patterned carrier wafers and methods of making and using the same |
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JP2016171124A (ja) * | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR20170015260A (ko) * | 2015-07-30 | 2017-02-08 | 셈테크 코포레이션 | 작은 z 치수 패키지를 형성하는 반도체 소자 및 방법 |
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KR20230162620A (ko) | 2021-03-29 | 2023-11-28 | 아지노모토 가부시키가이샤 | 회로 기판의 제조 방법 |
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