JP2020025054A - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 242
- 238000004519 manufacturing process Methods 0.000 title claims description 54
- 210000000746 body region Anatomy 0.000 claims abstract description 141
- 150000004767 nitrides Chemical group 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 50
- 239000011800 void material Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
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- 239000004020 conductor Substances 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 3
- 239000012535 impurity Substances 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 23
- 230000005684 electric field Effects 0.000 description 21
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 19
- 239000000758 substrate Substances 0.000 description 17
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 14
- 229910002601 GaN Inorganic materials 0.000 description 13
- 238000005304 joining Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
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- 238000007740 vapor deposition Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
Description
図1に、第1実施形態の半導体装置1の要部断面図を示す。半導体装置1は、窒化物半導体層20、窒化物半導体層20の裏面を被覆するドレイン電極32、窒化物半導体層20の表面を被覆するソース電極34、及び、窒化物半導体層20の表面上の一部に設けられている絶縁ゲート部36を備えている。窒化物半導体層20は、n+型のドレイン領域21、n型のドリフト領域22、n型のJFET領域23、p型のボディ領域24、n+型のソース領域25、及び、p+型のボディコンタクト領域26を有している。
次に、半導体装置1の製造方法を説明する。まず、図2Aに示されるように、エピタキシャル成長技術を利用して、窒化物半導体基板12の表面からn型GaNのn型窒化物半導体層14、p型GaNの高濃度ボディ領域24a及びp型GaNの低濃度ボディ領域24bをこの順で積層し、第1窒化物半導体層120を準備する。次に、p型不純物を活性化させるために、アニール処理(約850℃、約5分)を実施する。窒化物半導体基板12は、厚さが約400μmであり、不純物濃度が約1×1018cm-3である。n型窒化物半導体層14は、厚さが約5.0μmであり、不純物濃度が約2×1016cm-3である。高濃度ボディ領域24aは、厚さが約0.5μmであり、不純物濃度が約2×1019cm-3である。低濃度ボディ領域24bは、厚さが約1.5μmであり、不純物濃度が約1×1018cm-3である。必要に応じて、窒化物半導体基板12とn型窒化物半導体層14の間に、厚さが約0.2μmであり、不純物濃度が約3×1018cm-3のn型GaNのバッファ層を形成してもよい。
図3に、第2実施形態の半導体装置2の要部断面図を示す。この半導体装置2では、空隙43が、窒化物半導体層20の表面に直交する方向から見たときに、JFET領域23の存在範囲内の一部に位置している。空隙43は、ドリフト領域22とJFET領域23の接合面、ドリフト領域22と高濃度ボディ領域24aの接合面、及び、JFET領域23と高濃度ボディ領域24aの接合面が交差する部分に対応して設けられており、その内壁面がドリフト領域22とJFET領域23と高濃度ボディ領域24aによって画定されている。詳細には、空隙43は、JFET領域23のうちのドリフト領域22側であって高濃度ボディ領域24a側の一部を除去して形成されている。このように、ドリフト領域22とJFET領域23と高濃度ボディ領域24aは、空隙43に露出している。半導体装置2でも、電界が集中する部分に対応して真空の空隙43が形成されているので、この電界が集中する部分での絶縁破壊が抑制される。
図4に、第3実施形態の半導体装置3の要部断面図を示す。この半導体装置3では、空隙44が、窒化物半導体層20の表面に直交する方向から見たときに、JFET領域23の存在範囲内の一部と高濃度ボディ領域24aの存在範囲内の一部を跨ぐように位置している。空隙44は、ドリフト領域22とJFET領域23の接合面、ドリフト領域22と高濃度ボディ領域24aの接合面、及び、JFET領域23と高濃度ボディ領域24aの接合面が交差する部分に対応して設けられており、その内壁面がドリフト領域22とJFET領域23と高濃度ボディ領域24aによって画定されている。詳細には、空隙43は、JFET領域23のうちのドリフト領域22側であって高濃度ボディ領域24a側の一部、及び、高濃度ボディ領域24aのうちのドリフト領域22側であってJFET領域23側の一部を除去して形成されている。このように、ドリフト領域22とJFET領域23と高濃度ボディ領域24aは、空隙44に露出している。半導体装置3でも、電界が集中する部分に対応して真空の空隙44が形成されているので、この電界が集中する部分での絶縁破壊が抑制される。
図5に、第4実施形態の半導体装置4の要部断面図を示す。この半導体装置4では、空隙46が、窒化物半導体層20の表面に直交する方向から見たときに、高濃度ボディ領域24aの存在範囲内の一部に位置している。空隙46は、ドリフト領域22とJFET領域23の接合面、ドリフト領域22と高濃度ボディ領域24aの接合面、及び、JFET領域23と高濃度ボディ領域24aの接合面が交差する部分に対応して設けられており、その内壁面がドリフト領域22とJFET領域23と高濃度ボディ領域24aによって画定されている。詳細には、空隙46は、高濃度ボディ領域24aのうちのドリフト領域22側であってJFET領域23側の一部を除去して形成されている。このように、ドリフト領域22とJFET領域23と高濃度ボディ領域24aは、空隙46に露出している。
次に、半導体装置4の製造方法を説明する。まず、図6Aに示されるように、エピタキシャル成長技術を利用して、窒化物半導体基板112の表面からn型GaNのn型窒化物半導体層114を成膜し、第1窒化物半導体層220を準備する。窒化物半導体基板112は、厚さが約400μmであり、不純物濃度が約1×1018cm-3である。n型窒化物半導体層114は、厚さが約7.0μmであり、不純物濃度が約2×1016cm-3である。必要に応じて、窒化物半導体基板112とn型窒化物半導体層114の間に、厚さが約0.2μmであり、不純物濃度が約3×1018cm-3のn型GaNのバッファ層を形成してもよい。
図7に、第5実施形態の半導体装置5の要部断面図を示す。この半導体装置5では、空隙47が、窒化物半導体層20の表面に直交する方向から見たときに、JFET領域23の存在範囲内の一部に位置している。空隙47は、ドリフト領域22とJFET領域23の接合面、ドリフト領域22と高濃度ボディ領域24aの接合面、及び、JFET領域23と高濃度ボディ領域24aの接合面が交差する部分に対応して設けられており、その内壁面がドリフト領域22とJFET領域23と高濃度ボディ領域24aによって画定されている。詳細には、空隙47は、JFET領域23のうちのドリフト領域22側であって高濃度ボディ領域24a側の一部を除去して形成されている。このように、ドリフト領域22とJFET領域23と高濃度ボディ領域24aは、空隙47に露出している。
次に、半導体装置5の製造方法を説明する。まず、図8Aに示されるように、第1窒化物半導体層320にトレンチTR1を形成するまでの工程は、図2A及び図2Bと同一である。次に、蒸着技術を利用して、トレンチTR1の内壁面にシリコン酸化膜74を成膜する。なお、シリコン酸化膜74は、犠牲膜の一例である。
20:窒化物半導体層
21:ドレイン領域
22:ドリフト領域
23:JFET領域
24:ボディ領域
24a:高濃度ボディ領域
24b:低濃度ボディ領域
25:ソース領域
26:ボディコンタクト領域
32:ドレイン電極
34:ソース電極
36:絶縁ゲート部
36a:ゲート絶縁膜
36b:ゲート電極
42,43,44,46,47:空隙
Claims (12)
- 半導体層と、
前記半導体層の一方の主面上に設けられているソース電極と、
前記半導体層の他方の主面上に設けられているドレイン電極と、
絶縁ゲート部と、を備えており、
前記半導体層は、
第1導電型のドリフト領域と、
前記ドリフト領域上に設けられている第1導電型のJFET領域と、
前記ドリフト領域上に設けられており、前記JFET領域に隣接している第2導電型のボディ領域と、
前記ボディ領域によって前記JFET領域から隔てられている第1導電型のソース領域と、を有しており、
前記絶縁ゲート部は、前記JFET領域と前記ソース領域を隔てている部分の前記ボディ領域に対向しており、
前記半導体層内には真空の空隙が形成されており、前記ドリフト領域と前記JFET領域と前記ボディ領域が前記空隙に露出する、半導体装置。 - 前記空隙は、前記半導体層の前記一方の主面に直交する方向から見たときに、前記ボディ領域の存在範囲内に位置している、請求項1に記載の半導体装置。
- 前記空隙に露出する前記ボディ領域の面は、前記空隙に向けて凸となるような曲面である、請求項2に記載の半導体装置。
- 前記空隙は、前記半導体層の前記一方の主面に直交する方向から見たときに、前記JFET領域の存在範囲内に位置している、請求項1に記載の半導体装置。
- 前記空隙に露出する前記JFET領域の面は、前記空隙に向けて凸となるような曲面である、請求項4に記載の半導体装置。
- 前記半導体層の材料が、窒化物半導体である、請求項1〜5のいずれか一項に記載の半導体装置。
- 第1導電型のJFET領域と第2導電型のボディ領域が一方の主面側に隣接して設けられている第1半導体層を準備する工程と、
前記第1半導体層の他方の主面側から前記JFET領域と前記ボディ領域が露出するまで前記第1半導体層を除去する工程と、
前記第1半導体層を除去して現れた面に、前記JFET領域と前記ボディ領域が露出する溝を形成する工程と、
前記溝を真空に維持しながら、前記溝を覆うように第1導電型のドリフト領域を形成することにより、前記ドリフト領域と前記JFET領域と前記ボディ領域が露出する空隙を形成する工程と、を備えている、半導体装置の製造方法。 - 前記第1半導体層を準備する工程は、
前記第1半導体層の前記一方の主面から前記JFET領域の一部を貫通するトレンチを形成する工程と、
前記トレンチの内壁面を被覆するように犠牲膜を形成する工程と、
前記トレンチの側面と底面の間に構成される角部に前記犠牲膜の一部が残存するように、前記犠牲膜を除去する工程と、
前記犠牲膜の一部が残存した状態で、前記トレンチを充填するように前記ボディ領域を形成する工程と、を有しており、
前記溝を形成する工程は、
残存している前記犠牲膜の一部を除去する工程、を有する、請求項7に記載の半導体装置の製造方法。 - 前記第1半導体層を準備する工程は、
前記第1半導体層の前記一方の主面から前記ボディ領域の一部を貫通するトレンチを形成する工程と、
前記トレンチの内壁面を被覆するように犠牲膜を形成する工程と、
前記トレンチの側面と底面の間に構成される角部に前記犠牲膜の一部が残存するように、前記犠牲膜を除去する工程と、
前記犠牲膜の一部が残存した状態で、前記トレンチを充填するように前記JFET領域を形成する工程と、を有しており、
前記溝を形成する工程は、
残存している前記犠牲膜の一部を除去する工程、を有する、請求項7に記載の半導体装置の製造方法。 - 前記第1半導体層の材料が、窒化物半導体である、請求項7〜9のいずれか一項に記載の半導体装置の製造方法。
- 前記空隙を形成する工程は、
前記ドリフト領域が設けられた第2半導体層を前記第1半導体層に接合する工程、を有している、請求項7〜10のいずれか一項に記載の半導体装置の製造方法。 - 前記第2半導体層の材料が、窒化物半導体である、請求項11に記載の半導体装置の製造方法。
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