JP2019515282A5 - - Google Patents

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Publication number
JP2019515282A5
JP2019515282A5 JP2018556862A JP2018556862A JP2019515282A5 JP 2019515282 A5 JP2019515282 A5 JP 2019515282A5 JP 2018556862 A JP2018556862 A JP 2018556862A JP 2018556862 A JP2018556862 A JP 2018556862A JP 2019515282 A5 JP2019515282 A5 JP 2019515282A5
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JP
Japan
Prior art keywords
pads
integrated circuit
test
pad
state
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Application number
JP2018556862A
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English (en)
Japanese (ja)
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JP2019515282A (ja
JP7004316B2 (ja
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Priority claimed from US15/143,454 external-priority patent/US9791505B1/en
Application filed filed Critical
Publication of JP2019515282A publication Critical patent/JP2019515282A/ja
Publication of JP2019515282A5 publication Critical patent/JP2019515282A5/ja
Priority to JP2021207633A priority Critical patent/JP7239913B2/ja
Application granted granted Critical
Publication of JP7004316B2 publication Critical patent/JP7004316B2/ja
Priority to JP2023023870A priority patent/JP7505845B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2018556862A 2016-04-29 2017-05-01 フルパッドカバレッジバウンダリスキャン Active JP7004316B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2021207633A JP7239913B2 (ja) 2016-04-29 2021-12-22 フルパッドカバレッジバウンダリスキャン
JP2023023870A JP7505845B2 (ja) 2016-04-29 2023-02-17 フルパッドカバレッジバウンダリスキャン

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/143,454 US9791505B1 (en) 2016-04-29 2016-04-29 Full pad coverage boundary scan
US15/143,454 2016-04-29
PCT/US2017/030359 WO2017190123A1 (en) 2016-04-29 2017-05-01 Full pad coverage boundary scan

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2021207633A Division JP7239913B2 (ja) 2016-04-29 2021-12-22 フルパッドカバレッジバウンダリスキャン

Publications (3)

Publication Number Publication Date
JP2019515282A JP2019515282A (ja) 2019-06-06
JP2019515282A5 true JP2019515282A5 (enExample) 2020-05-21
JP7004316B2 JP7004316B2 (ja) 2022-02-04

Family

ID=60022604

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2018556862A Active JP7004316B2 (ja) 2016-04-29 2017-05-01 フルパッドカバレッジバウンダリスキャン
JP2021207633A Active JP7239913B2 (ja) 2016-04-29 2021-12-22 フルパッドカバレッジバウンダリスキャン
JP2023023870A Active JP7505845B2 (ja) 2016-04-29 2023-02-17 フルパッドカバレッジバウンダリスキャン

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2021207633A Active JP7239913B2 (ja) 2016-04-29 2021-12-22 フルパッドカバレッジバウンダリスキャン
JP2023023870A Active JP7505845B2 (ja) 2016-04-29 2023-02-17 フルパッドカバレッジバウンダリスキャン

Country Status (5)

Country Link
US (4) US9791505B1 (enExample)
JP (3) JP7004316B2 (enExample)
KR (1) KR102247968B1 (enExample)
CN (2) CN109154633B (enExample)
WO (1) WO2017190123A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan
DE112019004344T5 (de) * 2018-08-31 2021-05-20 Nvidia Corporation Testsystem zur Ausführung eines integrierten Selbsttests im Einsatz für Fahrzeuganwendungen
US11249134B1 (en) * 2020-10-06 2022-02-15 Qualcomm Incorporated Power-collapsible boundary scan
CN112526327B (zh) * 2020-10-28 2022-07-08 深圳市紫光同创电子有限公司 边界扫描测试方法及存储介质
CN113589154B (zh) * 2021-08-31 2025-07-08 成都海光集成电路设计有限公司 一种边界扫描电路
CN113655376B (zh) * 2021-09-13 2025-04-04 成都海光集成电路设计有限公司 一种扫描测试交换网络和扫描测试方法
CN113938125B (zh) * 2021-10-19 2023-02-24 浙江大学 多通道可配置可测试与修调的数字信号隔离器

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2673888B2 (ja) * 1988-01-11 1997-11-05 クロスチェック・テクノロジイ・インコーポレーテッド 集積回路を電気的に試験する方法および装置
JP2561164B2 (ja) * 1990-02-26 1996-12-04 三菱電機株式会社 半導体集積回路
JP2627464B2 (ja) * 1990-03-29 1997-07-09 三菱電機株式会社 集積回路装置
US5513188A (en) * 1991-09-10 1996-04-30 Hewlett-Packard Company Enhanced interconnect testing through utilization of board topology data
JP2741119B2 (ja) * 1991-09-17 1998-04-15 三菱電機株式会社 バイパススキャンパスおよびそれを用いた集積回路装置
US5231314A (en) * 1992-03-02 1993-07-27 National Semiconductor Corporation Programmable timing circuit for integrated circuit device with test access port
US5270642A (en) * 1992-05-15 1993-12-14 Hewlett-Packard Company Partitioned boundary-scan testing for the reduction of testing-induced damage
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
US5404359A (en) * 1992-06-29 1995-04-04 Tandem Computers Incorporated Fail safe, fault tolerant circuit for manufacturing test logic on application specific integrated circuits
US5477545A (en) * 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
JPH0862294A (ja) * 1994-08-25 1996-03-08 Mitsubishi Electric Corp 半導体装置及び半導体装置のテスト方法
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US6173428B1 (en) * 1994-11-16 2001-01-09 Cray Research, Inc. Apparatus and method for testing using clocked test access port controller for level sensitive scan designs
US5615217A (en) * 1994-12-01 1997-03-25 International Business Machines Corporation Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components
WO1996041205A1 (en) * 1995-06-07 1996-12-19 Samsung Electronics Co., Ltd. Method and apparatus for testing a megacell in an asic using jtag
JPH0934864A (ja) * 1995-07-14 1997-02-07 Sharp Corp シングルチップマイクロコンピュータ
US5710779A (en) * 1996-04-09 1998-01-20 Texas Instruments Incorporated Real time data observation method and apparatus
US5974578A (en) * 1996-08-06 1999-10-26 Matsushita Electronics Corporation Integrated circuit and test method therefor
JP3193979B2 (ja) * 1996-08-06 2001-07-30 松下電器産業株式会社 集積回路及びそのテスト方法
US5804996A (en) * 1997-02-13 1998-09-08 Ramtron International Corporation Low-power non-resetable test mode circuit
JP3835884B2 (ja) * 1997-04-30 2006-10-18 株式会社 沖マイクロデザイン 半導体集積回路の入力回路
WO1999052033A1 (fr) * 1998-04-03 1999-10-14 Hitachi, Ltd. Dispositif semi-conducteur
JP3866444B2 (ja) * 1998-04-22 2007-01-10 東芝マイクロエレクトロニクス株式会社 半導体装置及びその内部信号モニタ方法
JPH11354594A (ja) * 1998-06-08 1999-12-24 Mitsubishi Electric Corp 半導体装置
US6430719B1 (en) * 1998-06-12 2002-08-06 Stmicroelectronics, Inc. General port capable of implementing the JTAG protocol
JP2000162277A (ja) * 1998-11-25 2000-06-16 Mitsubishi Electric Corp 半導体集積回路
US6266793B1 (en) * 1999-02-26 2001-07-24 Intel Corporation JTAG boundary scan cell with enhanced testability feature
JP2000275303A (ja) * 1999-03-23 2000-10-06 Mitsubishi Electric Corp バウンダリスキャンテスト方法及びバウンダリスキャンテスト装置
JP4201952B2 (ja) * 2000-03-17 2008-12-24 川崎マイクロエレクトロニクス株式会社 半導体集積回路
JP4480238B2 (ja) * 2000-07-18 2010-06-16 Ｏｋｉセミコンダクタ株式会社 半導体装置
US6851079B1 (en) * 2001-03-28 2005-02-01 Lsi Logic Corporation Jtag test access port controller used to control input/output pad functionality
JP4734762B2 (ja) * 2001-05-25 2011-07-27 ソニー株式会社 メモリカード
US7036061B2 (en) * 2001-08-28 2006-04-25 Intel Corporation Structural input levels testing using on-die levels generators
JP4309086B2 (ja) * 2001-12-20 2009-08-05 株式会社ルネサステクノロジ 半導体集積回路装置
US6925583B1 (en) * 2002-01-09 2005-08-02 Xilinx, Inc. Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device
JP2003228999A (ja) * 2002-02-01 2003-08-15 Rohm Co Ltd 半導体記憶装置
TW558640B (en) * 2002-02-06 2003-10-21 Guo-Jan Peng Debugging and positioning method of chip and equipment thereof
US20030163773A1 (en) * 2002-02-26 2003-08-28 O'brien James J. Multi-core controller
CN100547425C (zh) * 2003-02-10 2009-10-07 Nxp股份有限公司 集成电路的测试
US7487419B2 (en) * 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
TW200708750A (en) * 2005-07-22 2007-03-01 Koninkl Philips Electronics Nv Testable integrated circuit, system in package and test instruction set
US7406642B1 (en) * 2005-10-03 2008-07-29 Altera Corporation Techniques for capturing signals at output pins in a programmable logic integrated circuit
US7398441B1 (en) * 2005-12-21 2008-07-08 Rockwell Collins, Inc. System and method for providing secure boundary scan interface access
EP1852706B1 (en) * 2006-05-04 2009-10-28 STMicroelectronics S.r.l. Adaptive scan compression architecture
JP5095273B2 (ja) * 2007-06-22 2012-12-12 株式会社東芝 制御装置
CN101470165A (zh) * 2007-12-28 2009-07-01 瑞昱半导体股份有限公司 微电子装置与管脚安排方法
US8230281B2 (en) * 2009-04-13 2012-07-24 Altera Corporation Techniques for boundary scan testing using transmitters and receivers
CN201876497U (zh) * 2010-10-26 2011-06-22 上海仪表厂有限责任公司 五路扫描电性能综合测试装置
US9110142B2 (en) * 2011-09-30 2015-08-18 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
CN103116123B (zh) * 2011-11-17 2015-04-08 华邦电子股份有限公司 集成电路
CN203733117U (zh) * 2011-12-14 2014-07-23 通用电气公司 接口连接主处理器与从处理器的系统
US8914693B2 (en) * 2012-02-15 2014-12-16 International Business Machines Corporation Apparatus for JTAG-driven remote scanning
US9389945B1 (en) * 2012-09-07 2016-07-12 Mentor Graphics Corporation Test access architecture for stacked dies
CN103091627B (zh) * 2013-01-09 2015-02-25 中国科学院微电子研究所 一种可配置的边界扫描寄存器链电路
CN104049203B (zh) * 2014-04-25 2017-02-15 三星半导体(中国)研究开发有限公司 具有边界扫描测试功能的管脚和包括该管脚的集成电路
US20160282414A1 (en) * 2015-03-23 2016-09-29 Netapp, Inc. Boundary scan testing with loopbacks
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan

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