KR102247968B1 - 전체 패드 커버리지 바운더리 스캔 - Google Patents
전체 패드 커버리지 바운더리 스캔 Download PDFInfo
- Publication number
- KR102247968B1 KR102247968B1 KR1020187034345A KR20187034345A KR102247968B1 KR 102247968 B1 KR102247968 B1 KR 102247968B1 KR 1020187034345 A KR1020187034345 A KR 1020187034345A KR 20187034345 A KR20187034345 A KR 20187034345A KR 102247968 B1 KR102247968 B1 KR 102247968B1
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- KR
- South Korea
- Prior art keywords
- pads
- test
- state
- signals
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000012360 testing method Methods 0.000 claims abstract description 106
- 210000004027 cell Anatomy 0.000 claims description 70
- 238000000034 method Methods 0.000 claims description 22
- 210000003888 boundary cell Anatomy 0.000 claims description 13
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 2
- 238000010998 test method Methods 0.000 claims 1
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 21
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 230000009471 action Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/143,454 | 2016-04-29 | ||
| US15/143,454 US9791505B1 (en) | 2016-04-29 | 2016-04-29 | Full pad coverage boundary scan |
| PCT/US2017/030359 WO2017190123A1 (en) | 2016-04-29 | 2017-05-01 | Full pad coverage boundary scan |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20180133926A KR20180133926A (ko) | 2018-12-17 |
| KR102247968B1 true KR102247968B1 (ko) | 2021-05-03 |
Family
ID=60022604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020187034345A Active KR102247968B1 (ko) | 2016-04-29 | 2017-05-01 | 전체 패드 커버리지 바운더리 스캔 |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US9791505B1 (enExample) |
| JP (3) | JP7004316B2 (enExample) |
| KR (1) | KR102247968B1 (enExample) |
| CN (2) | CN113484719B (enExample) |
| WO (1) | WO2017190123A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9791505B1 (en) * | 2016-04-29 | 2017-10-17 | Texas Instruments Incorporated | Full pad coverage boundary scan |
| JP7385651B2 (ja) * | 2018-08-31 | 2023-11-22 | エヌビディア コーポレーション | 自動車用途のための配置中にビルトイン・セルフテストを実行するためのテスト・システム |
| US11249134B1 (en) * | 2020-10-06 | 2022-02-15 | Qualcomm Incorporated | Power-collapsible boundary scan |
| CN112526327B (zh) * | 2020-10-28 | 2022-07-08 | 深圳市紫光同创电子有限公司 | 边界扫描测试方法及存储介质 |
| CN113589154B (zh) * | 2021-08-31 | 2025-07-08 | 成都海光集成电路设计有限公司 | 一种边界扫描电路 |
| CN113655376B (zh) * | 2021-09-13 | 2025-04-04 | 成都海光集成电路设计有限公司 | 一种扫描测试交换网络和扫描测试方法 |
| CN113938125B (zh) * | 2021-10-19 | 2023-02-24 | 浙江大学 | 多通道可配置可测试与修调的数字信号隔离器 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000011698A (ja) | 1998-04-22 | 2000-01-14 | Toshiba Microelectronics Corp | 半導体装置及びその内部信号モニタ方法 |
| JP2001267506A (ja) | 2000-03-17 | 2001-09-28 | Kawasaki Steel Corp | 半導体集積回路 |
| JP2002033455A (ja) | 2000-07-18 | 2002-01-31 | Oki Electric Ind Co Ltd | 半導体装置 |
| JP2003187600A (ja) | 2001-12-20 | 2003-07-04 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JP2003228999A (ja) | 2002-02-01 | 2003-08-15 | Rohm Co Ltd | 半導体記憶装置 |
Family Cites Families (52)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2673888B2 (ja) * | 1988-01-11 | 1997-11-05 | クロスチェック・テクノロジイ・インコーポレーテッド | 集積回路を電気的に試験する方法および装置 |
| JP2561164B2 (ja) * | 1990-02-26 | 1996-12-04 | 三菱電機株式会社 | 半導体集積回路 |
| JP2627464B2 (ja) * | 1990-03-29 | 1997-07-09 | 三菱電機株式会社 | 集積回路装置 |
| US5513188A (en) * | 1991-09-10 | 1996-04-30 | Hewlett-Packard Company | Enhanced interconnect testing through utilization of board topology data |
| JP2741119B2 (ja) * | 1991-09-17 | 1998-04-15 | 三菱電機株式会社 | バイパススキャンパスおよびそれを用いた集積回路装置 |
| US5231314A (en) * | 1992-03-02 | 1993-07-27 | National Semiconductor Corporation | Programmable timing circuit for integrated circuit device with test access port |
| US5270642A (en) * | 1992-05-15 | 1993-12-14 | Hewlett-Packard Company | Partitioned boundary-scan testing for the reduction of testing-induced damage |
| US5471481A (en) * | 1992-05-18 | 1995-11-28 | Sony Corporation | Testing method for electronic apparatus |
| US5404359A (en) * | 1992-06-29 | 1995-04-04 | Tandem Computers Incorporated | Fail safe, fault tolerant circuit for manufacturing test logic on application specific integrated circuits |
| US5477545A (en) * | 1993-02-09 | 1995-12-19 | Lsi Logic Corporation | Method and apparatus for testing of core-cell based integrated circuits |
| JPH0862294A (ja) * | 1994-08-25 | 1996-03-08 | Mitsubishi Electric Corp | 半導体装置及び半導体装置のテスト方法 |
| US5592493A (en) * | 1994-09-13 | 1997-01-07 | Motorola Inc. | Serial scan chain architecture for a data processing system and method of operation |
| US6173428B1 (en) * | 1994-11-16 | 2001-01-09 | Cray Research, Inc. | Apparatus and method for testing using clocked test access port controller for level sensitive scan designs |
| US5615217A (en) * | 1994-12-01 | 1997-03-25 | International Business Machines Corporation | Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components |
| KR100248258B1 (ko) * | 1995-06-07 | 2000-03-15 | 윤종용 | 제이택을이용한응용주문형집적회로에서의메가셀테스트방법및장치 |
| JPH0934864A (ja) * | 1995-07-14 | 1997-02-07 | Sharp Corp | シングルチップマイクロコンピュータ |
| US5710779A (en) * | 1996-04-09 | 1998-01-20 | Texas Instruments Incorporated | Real time data observation method and apparatus |
| US5974578A (en) * | 1996-08-06 | 1999-10-26 | Matsushita Electronics Corporation | Integrated circuit and test method therefor |
| JP3193979B2 (ja) * | 1996-08-06 | 2001-07-30 | 松下電器産業株式会社 | 集積回路及びそのテスト方法 |
| US5804996A (en) * | 1997-02-13 | 1998-09-08 | Ramtron International Corporation | Low-power non-resetable test mode circuit |
| JP3835884B2 (ja) * | 1997-04-30 | 2006-10-18 | 株式会社 沖マイクロデザイン | 半導体集積回路の入力回路 |
| KR20010042264A (ko) * | 1998-04-03 | 2001-05-25 | 가나이 쓰토무 | 반도체장치 |
| JPH11354594A (ja) * | 1998-06-08 | 1999-12-24 | Mitsubishi Electric Corp | 半導体装置 |
| US6430719B1 (en) | 1998-06-12 | 2002-08-06 | Stmicroelectronics, Inc. | General port capable of implementing the JTAG protocol |
| JP2000162277A (ja) * | 1998-11-25 | 2000-06-16 | Mitsubishi Electric Corp | 半導体集積回路 |
| US6266793B1 (en) * | 1999-02-26 | 2001-07-24 | Intel Corporation | JTAG boundary scan cell with enhanced testability feature |
| JP2000275303A (ja) * | 1999-03-23 | 2000-10-06 | Mitsubishi Electric Corp | バウンダリスキャンテスト方法及びバウンダリスキャンテスト装置 |
| US6851079B1 (en) * | 2001-03-28 | 2005-02-01 | Lsi Logic Corporation | Jtag test access port controller used to control input/output pad functionality |
| JP4734762B2 (ja) | 2001-05-25 | 2011-07-27 | ソニー株式会社 | メモリカード |
| US7036061B2 (en) * | 2001-08-28 | 2006-04-25 | Intel Corporation | Structural input levels testing using on-die levels generators |
| US6925583B1 (en) * | 2002-01-09 | 2005-08-02 | Xilinx, Inc. | Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device |
| TW558640B (en) * | 2002-02-06 | 2003-10-21 | Guo-Jan Peng | Debugging and positioning method of chip and equipment thereof |
| US20030163773A1 (en) * | 2002-02-26 | 2003-08-28 | O'brien James J. | Multi-core controller |
| CN100547425C (zh) * | 2003-02-10 | 2009-10-07 | Nxp股份有限公司 | 集成电路的测试 |
| US7487419B2 (en) * | 2005-06-15 | 2009-02-03 | Nilanjan Mukherjee | Reduced-pin-count-testing architectures for applying test patterns |
| TW200708750A (en) * | 2005-07-22 | 2007-03-01 | Koninkl Philips Electronics Nv | Testable integrated circuit, system in package and test instruction set |
| US7406642B1 (en) * | 2005-10-03 | 2008-07-29 | Altera Corporation | Techniques for capturing signals at output pins in a programmable logic integrated circuit |
| US7398441B1 (en) * | 2005-12-21 | 2008-07-08 | Rockwell Collins, Inc. | System and method for providing secure boundary scan interface access |
| DE602006010031D1 (de) * | 2006-05-04 | 2009-12-10 | St Microelectronics Srl | Adaptive Scan-compression Architektur |
| JP5095273B2 (ja) | 2007-06-22 | 2012-12-12 | 株式会社東芝 | 制御装置 |
| CN101470165A (zh) * | 2007-12-28 | 2009-07-01 | 瑞昱半导体股份有限公司 | 微电子装置与管脚安排方法 |
| US8230281B2 (en) * | 2009-04-13 | 2012-07-24 | Altera Corporation | Techniques for boundary scan testing using transmitters and receivers |
| CN201876497U (zh) * | 2010-10-26 | 2011-06-22 | 上海仪表厂有限责任公司 | 五路扫描电性能综合测试装置 |
| US9110142B2 (en) * | 2011-09-30 | 2015-08-18 | Freescale Semiconductor, Inc. | Methods and apparatus for testing multiple-IC devices |
| CN103116123B (zh) * | 2011-11-17 | 2015-04-08 | 华邦电子股份有限公司 | 集成电路 |
| WO2013086704A1 (en) * | 2011-12-14 | 2013-06-20 | General Electric Company | Systems and methods for interfacing master and slave processors |
| US8914693B2 (en) * | 2012-02-15 | 2014-12-16 | International Business Machines Corporation | Apparatus for JTAG-driven remote scanning |
| US9389945B1 (en) * | 2012-09-07 | 2016-07-12 | Mentor Graphics Corporation | Test access architecture for stacked dies |
| CN103091627B (zh) * | 2013-01-09 | 2015-02-25 | 中国科学院微电子研究所 | 一种可配置的边界扫描寄存器链电路 |
| CN104049203B (zh) * | 2014-04-25 | 2017-02-15 | 三星半导体(中国)研究开发有限公司 | 具有边界扫描测试功能的管脚和包括该管脚的集成电路 |
| US20160282414A1 (en) * | 2015-03-23 | 2016-09-29 | Netapp, Inc. | Boundary scan testing with loopbacks |
| US9791505B1 (en) * | 2016-04-29 | 2017-10-17 | Texas Instruments Incorporated | Full pad coverage boundary scan |
-
2016
- 2016-04-29 US US15/143,454 patent/US9791505B1/en active Active
-
2017
- 2017-05-01 CN CN202110742245.1A patent/CN113484719B/zh active Active
- 2017-05-01 WO PCT/US2017/030359 patent/WO2017190123A1/en not_active Ceased
- 2017-05-01 KR KR1020187034345A patent/KR102247968B1/ko active Active
- 2017-05-01 CN CN201780031966.3A patent/CN109154633B/zh active Active
- 2017-05-01 JP JP2018556862A patent/JP7004316B2/ja active Active
- 2017-10-02 US US15/722,975 patent/US10274538B2/en active Active
-
2019
- 2019-04-10 US US16/380,182 patent/US10983161B2/en active Active
-
2021
- 2021-03-30 US US17/217,391 patent/US11821945B2/en active Active
- 2021-12-22 JP JP2021207633A patent/JP7239913B2/ja active Active
-
2023
- 2023-02-17 JP JP2023023870A patent/JP7505845B2/ja active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000011698A (ja) | 1998-04-22 | 2000-01-14 | Toshiba Microelectronics Corp | 半導体装置及びその内部信号モニタ方法 |
| JP2001267506A (ja) | 2000-03-17 | 2001-09-28 | Kawasaki Steel Corp | 半導体集積回路 |
| JP2002033455A (ja) | 2000-07-18 | 2002-01-31 | Oki Electric Ind Co Ltd | 半導体装置 |
| JP2003187600A (ja) | 2001-12-20 | 2003-07-04 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JP2003228999A (ja) | 2002-02-01 | 2003-08-15 | Rohm Co Ltd | 半導体記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109154633A (zh) | 2019-01-04 |
| US20210215757A1 (en) | 2021-07-15 |
| CN113484719B (zh) | 2025-03-14 |
| US20180045778A1 (en) | 2018-02-15 |
| US20190235020A1 (en) | 2019-08-01 |
| US10983161B2 (en) | 2021-04-20 |
| JP2022043194A (ja) | 2022-03-15 |
| US10274538B2 (en) | 2019-04-30 |
| JP7239913B2 (ja) | 2023-03-15 |
| JP7505845B2 (ja) | 2024-06-25 |
| CN113484719A (zh) | 2021-10-08 |
| WO2017190123A1 (en) | 2017-11-02 |
| JP2019515282A (ja) | 2019-06-06 |
| US9791505B1 (en) | 2017-10-17 |
| US11821945B2 (en) | 2023-11-21 |
| US20170315174A1 (en) | 2017-11-02 |
| CN109154633B (zh) | 2021-08-24 |
| KR20180133926A (ko) | 2018-12-17 |
| JP2023063323A (ja) | 2023-05-09 |
| JP7004316B2 (ja) | 2022-02-04 |
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Patent event code: PA02012R01D Patent event date: 20200423 Comment text: Request for Examination of Application |
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