Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2851—Testing of integrated circuits [IC]
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318572—Input/Output interfaces
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/31712—Input or output aspects
  • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3177—Testing of logic operation, e.g. by logic analysers

Definitions

• This relates to boundary scan of integrated circuits and printed circuit boards.
• Boundary scan is a method and related circuiting for testing logic, memories, and other circuits on an integrated circuit (IC) or printed circuit board (PCB).
• IC integrated circuit
• PCB printed circuit board
• TAP dedicated test access port
• the TAP signals are useful to determine whether an IC is properly functioning, whether it is connected to the PCB, and also for debugging by observing IC pin states or measured voltages. Testing may be achieved at the time of manufacture, such as by automated testing equipment (ATE), and subsequent testing in the field (e.g., after a device has been sold or located in the marketplace). Additional details and standardization in connection with boundary scan were developed by the Joint Test Action Group (JTAG) and are specified in an IEEE 1149 standard and its .x sub-standards.
• JTAG Joint Test Action Group
• FIG. 1 illustrates an electrical block diagram of an IC 10 having a conventional boundary scan architecture.
• IC 10 is shown to include: a test access port TAP controller 12 for interfacing with TAP signals and as relating to JTAG testing; and IC functional circuitry 14, sometimes referred to as a core, which is a general depiction of the various circuit functions of IC 10, apart from JTAG testing.
• IC 10 also includes a number of I/O pads Po through Pi 5 , shown at various locations around the perimeter of the device. Pads P 0 through P 4 carry respective and known JTAG TAP related signals, as shown in the following Table 1.
• pad P 4 allows input of JTAG test data and pad P 0 allows output thereof, while the remaining pads Pi through P 3 provide signals to TAP controller 12.
• An instruction register 16 stores a current JTAG instruction, typically to indicate the operation to take with respect to signals that are received (e.g., defining to which data register signals should pass).
• a bypass register 18 is a single bit register that permits TDI to bypass a chain of cells C 0 through C 15 so as to pass directly from input to output.
• An ID register 20 is for storing the ID code and revision number for IC 10, thereby allowing IC 10 to be linked to a file that stores boundary scan configuration information for IC 10.
• each of the remaining IC pads P 5 through Pis is connected through a respective boundary scan cell C 5 through C 15 , to functional circuitry 14.
• such pads represent the I/O of IC 10, in connection with its intended operation as achieved by functional circuitry 14.
• each of scan cells C 5 through C 15 is connected to at least one other scan cell, thereby forming a scan chain.
• data may be input by a respective pad to each cell, or captured in each cell from functional circuitry 14, and then such data may be successively shifted along the chain, so that it is output from the last such cell C 15 as TDO information. Therefore, in this manner, the I/O connectivity and data states from functional circuitry 14 may be evaluated to confirm proper operation of IC 10.
• an integrated circuit includes functional circuitry and testing circuitry.
• the integrated circuit also includes a set of pads operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry.
• the integrated circuit also includes a second set of pads, differing from the set of pads, operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the set of pads.
• FIG. 1 illustrates an electrical block diagram of an IC 10 having a conventional boundary scan architecture.
• FIG. 2a illustrates an electrical block diagram of an IC 200 according to an example embodiment and in a first switched state for receiving a first set of JTAG test signals.
• FIG. 2b illustrates an electrical block diagram of the IC 200 of FIG. 2a and in a second switched state for receiving a second set of JTAG test signals.
• FIG. 3 illustrates a flow chart of an example method 300 of operation of IC 200.
• FIG. 4 illustrates an electrical block diagram of an alternative example embodiment IC
• FIG. 5 illustrates a structure for a cell C x that may be used for cells in IC 200' of FIG. 4.
• FIGS. 2a and 2b illustrate an electrical block diagram of an IC 200 according to an example embodiment.
• IC 200 includes various functional blocks comparable to those described hereinabove in connection with FIG. 1. For clarity, those blocks in FIGS. 2a and 2b are numbered by adding 200 to the reference number of FIG. 1.
• IC 200 in connection with processing JTAG signals and IC functionality, includes a TAP controller 212, functional circuitry (or core) 214, an instruction register 216, a bypass register 218, and an ID register 220.
• such blocks operate in conjunction with a set of JTAG signals from two different respective sets of pads (e.g., pins).
• pads e.g., pins
• IC 200 is operable in two different states, each of which is achieved with different switched signal paths, where FIG. 2a indicates a first such state indicated in a binary sense as a state of 0, and where FIG. 2b indicates a second such state indicated in a binary sense as a state of 1.
• states may be implemented by way of a state machine or comparable control, whereby the two states combined permit a full JT AG boundary scan of all pads of IC 200.
• IC 200 includes a number of pads Po through Pi 5 , so that example IC 200 is a 16-pin device. Further, a respective boundary scan cell C 0 through C 15 exists for each pad, thereby forming a boundary cell scan chain. Thus, in an example embodiment, each device pad has a corresponding boundary scan cell for reasons further described hereinbelow, in contrast to conventional techniques in which fixed JTAG pads do not have corresponding boundary scan cells (such as represented in the example of FIG. 1).
• a first set of pads namely pads Po through P 4 , are shown in FIG. 2a for receiving a first set of JTAG signals, as summarized in the following Table 2.
• each of the Table 2 pads P 0 through P 4 is connected to a respective switching element S 0 through S 4 so that in a first state as shown in FIG. 2a, each such switching element interconnects the pad so that its respective JTAG signal is appropriately routed to achieve JTAG testing. Therefore, in this first state: (i) pads Pi through P 3 are connected to TAP controller 212; (ii) pad Po is connected to receive data as TDOo from boundary scan cell C 15 , the last cell in the sequence of cells forming the boundary chain as configured in FIG.
• pad P 4 is connected so that its TDI 0 signal may be input, via a multiplexer 222 and switching element S 222 , to the boundary scan chain, starting at boundary scan cell C 5 , and also that signal is connected to instruction register 216, bypass register 218, and ID register 220.
• IC 200 as shown in FIG. 2a also includes a second set of pads, namely pads P 5 through P 9 , each of which is connected to a respective switching element S 5 through Sg so that in the first state, as shown in FIG. 2a, each such switching element interconnects the pad to a respective boundary scan cell in the scan cell chain, as summarized in the following Table 3.
• each of boundary cells C 5 through Cg provides an exclusive pass-through connectivity path between a respective pad, through the cell, to functional circuitry 214.
• "exclusive" indicates that each boundary pad permits only pass-through between one respective pin and functional circuitry 214. Therefore, such connectivity allows signals from either the pad or functional circuitry 214 to be captured in a respective cell, and the signal then may be shifted to a next successive cell, in a sequential manner, so that ultimately the signal is provided as output data TDO from the scan cell chain.
• IC 200 also includes pads beyond those in the first or second set of pads, where such additional pads may therefore be considered a third set of pads, which are not operable to receive JTAG signals.
• this third set of pads is shown as pads P 10 through Pi 5 .
• Each pad in the third set of pads preferably is directly connected, that is without a switching element as are the first and second set of pads, to a respective and exclusive pass-through boundary scan cell in the chain, as summarized in the following Table 4.
• the exclusive connectivity path between a respective pad, through the cell, to functional circuitry 214 allows signals from either the pad or functional circuitry 214 to be captured in a respective cell, and the signal may then be shifted to a next successive cell, in a sequential manner, so that ultimately the signal is provided as output data TDO from the scan cell chain.
• boundary cell C 15 is also output to the input of a de-multiplexer 224, which has a first output that, for a 0 state, connects the de-multiplexer input, via switching element So, to pad Po, so that in that state the output of cell C 15 is connected to pad Po.
• de-multiplexer 224 also has a second output that, for a 1 state, connects the de-multiplexer input to boundary scan cell Co.
• each of the outputs of instruction register 216, bypass register 218, and ID register 220 is connected to an input of a multiplexer 226, which has a first output that, for a 0 state, connects the de-multiplexer input to the input of multiplexer 224. Therefore, as described hereinabove, the latter during a 0 state connects its input to pin P 0 (as TDO 0 ) so that, during this state, the outputs of those registers may be connected to pin P 0 .
• IC 200 is shown in a second state, indicated with the number 1 corresponding to the position of various switch positions and de-multiplexer selections. Therefore, in this regard, the signal path for the scan chain of boundary cells from FIG. 2a is switched to a different path in FIG. 2b, thereby establishing that the scan chain is configurable in the sense that, in the first state, signals from a first set of pads (e.g., Po through P 4 ) do not pass to respective boundary cells, and in the second state, signals from a second set of pads (e.g., P 5 through P 9 ) do not pass to respective boundary cells. Therefore, in this regard, in FIG. 2b, a second set of pads receives a second set of JTAG signals, as summarized in the following Table 5. Table 5
• Each second state JTAG signal is connected to a respective switching element so that in the second state, as shown in FIG. 2b, each such switching element interconnects a pad, so that its respective JTAG signal is appropriately routed to achieve JTAG testing. Further, the routing bypasses the pass-through boundary scan cell to which such pads are respectively exclusively connected (i.e., cells C 5 through C 9 ) in state 0. Therefore, in this second state: (i) pads P 6 through P 8 are connected to TAP controller 212; (ii) pad P 5 is connected to receive, via multiplexer 222 and switch element S 5 data as TDOi from boundary scan cell C 4 , the last cell in the sequence of cells forming the boundary chain as configured in FIG.
• pad Pg is connected so that its TDIi signal may be input, via multiplexer 228, to the boundary scan chain, starting at boundary scan cell C 10 , and also that signal is connected to instruction register 216, bypass register 218, and ID register 220.
• IC 200 also includes the first set of pads. But due to the change in the connectivity to the configurable scan chain of boundary cells, each pad in the first set of pads, namely pads P 0 through P 4 , is in the second state connected, via a respective switching element S 0 through S 4 , to a respective boundary scan cell in the scan cell chain, as summarized in the following Table 6.
• each of boundary cells C 0 through C is also connected to functional circuitry 214.
• IC 200 again includes pads beyond those in the first or second set of pads, where such additional pads may therefore be considered a third set of pads, which are not operable to receive JTAG signals.
• this third set of pads is shown in FIG. 2b as pads P 10 through Pi 5 , each directly connected to a respective boundary scan cell in the chain, as summarized in Table 4 hereinabove.
• FIG. 3 illustrates a flow chart of an example method 300 of operation of IC 200.
• Method 300 may be achieved by way of a state machine included as part of TAP controller 212 or by other circuitry and control, either located singularly on IC 200 or in part external from it, such as with automated testing equipment (ATE).
• Method 300 commences with a JTAG testing commencement step 310, where by way of example such testing may be: at a manufacturer location, such as via ATE; or later in the field, either at the IC or PCB level.
• step 310 may occur when IC 200 is powered on, that is, as part of the power on reset procedure.
• step 320 IC 200 is operated in the first state 0 described hereinabove, in which case the switching element, multiplexing and de-multiplexing is as shown in FIG. 2a.
• a first set of JTAG signals e.g., four or five signals, per contemporary standards
• Table 2 hereinabove provides an example for this first set of JTAG signals.
• pad P 4 can introduce TDI data to the boundary scan chain, which in state 0 is configured to begin with cell C 5 and proceed through cell C 15 , and signal states may be: transferred between those cells and functional circuitry 214; and advanced along the configurable scan chain and produced as TDO data that is output via pad P 0 .
• Other JTAG testing also may be achieved during and with the configured boundary chain of step 320.
• step 330 IC 200 is operated in the second state 1 described hereinabove, in which case the switching elements, multiplexing and de-multiplexing is as shown in FIG. 2b.
• a second set of JTAG signals (e.g., four or five signals, per contemporary standards) is applied to a second set of pads, differing from the first set, and that in the given state are not connected to respective exclusive pass-through boundary chain cells, where this second set of JTAG signals also are appropriately routed based on the signal and as described hereinabove.
• Table 5 hereinabove provides an example for this second set of JTAG signals.
• JTAG testing is then performed with respect to at least those pads that were JTAG-connected in state 0, those being pads P 0 through P 4 .
• testing can be repeated (or alternative testing performed) with respect to the third set of pads, that is, pads P 10 through Pi 5 .
• pad P 9 can introduce TDI data to the boundary scan chain, which in state 1 is configured to begin with cell C 10 , continue through C 15 , and proceed back to and include cells Co through C 4 , but to exclude the cells (i.e., C 5 though C9) corresponding to those pads receiving JTAG signals.
• step 330 (a) in step 320, a first set of pads is used for receiving JTAG signals to test pads not in the first set; and (b) in step 330, a second set of pads, differing from the first set of pads, may be used for receiving JTAG signals to test the first set of pads.
• step 340 the second set of pads of IC 200 is re-configured back to the state 0 configuration, after which IC 200 may be operated according to the device specifications and the pad assignments for each pad. Therefore, in this respect, the second set of pads for IC 200 may be dual purpose pads, serving during testing as JTAG pads (in state 1 testing). After re-configuration in step 340, those pads are connected through respective scan cells to functional circuitry 214. Thereafter, method 300 concludes in step 350.
• FIG. 4 illustrates an alternative example embodiment IC 200', which shares various functional and structural aspects with the IC 200 described hereinabove.
• an IC is provided with: (i) a first set of pads operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry; and (ii) a second set of pads, differing from the first set of pads, operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
• the alternating sets of pads are facilitated with a switching circuit 230 to which the two sets of pads are connected, whereby switching circuit 230 may communicate signals between the pads and functional circuitry 214 and tap controller 212.
• tap controller 212 is operable to bi-directionally communicate with any of instruction register 216, bypass register 218, and ID register 220, so both of the two sets of pads (one for the first state, one for the second state) permit JTAG signals to be multiplexed in circuit 230, so that a single output set of JTAG signals drives the TAP logic (e.g., by coupling them to tap controller 212, which may then further bi-directionally communicate as needed with ID register 220, bypass register 218 and instruction register 216) and supports any other JTAG functionality.
• FIG. 5 illustrates a structure for a cell C x that may be used for the output and serial chain path of any of cells Co through C 15 in IC 200' of FIG. 4, where comparable circuitry or a portion thereof likewise may be implemented for the input path thereof.
• the entire boundary scan chain may be the same across different configurations of shared pads, with additional structure as now described ensuring that values shifted between cells that correspond to respective pads being used for JTAG do not propagate and affect the pads.
• Cell C x includes the following input or control signals:
• parallel input data from a functional pin muxing module (that may be included as part of functional circuitry 214) whereby signals related to functional use case (e.g., SPI, UART. . . ) are multiplexed as part of functional pin muxing module, and this signal is a first data input to a multiplexer 240, where a second data input to multiplexer 240 is the serial chain data from the preceding cell C x- i in the scan chain. Also, parallel input is input as a first data input to a multiplexer 242, where the second data input to multiplexer 242 is the output of a multiplexer 244.
• a functional pin muxing module that may be included as part of functional circuitry 214) whereby signals related to functional use case (e.g., SPI, UART. . . ) are multiplexed as part of functional pin muxing module, and this signal is a first data input to a multiplexer 240, where a second data input to multiplexer 240 is the
• • parallel input tpm data from a test pin muxing module, whereby signals related to test use case (e.g., scan, dmled, . . .) are multiplexed as part of test pin muxing module, and this signal is a first data input to multiplexer 244, where the second data input to multiplexer 242 is the output of a multiplexer 246.
• signals related to test use case e.g., scan, dmled, . . .
• top bsc shift controls multiplexer 240 to select between either the parallel input signal or the shifted data from the preceding cell C x- i in the scan chain.
• clock dr clocks a serial register flip flop 248 to clock in the data from the output of multiplexer 240 while outputting data to a latch out register flip flop 250.
• top bsc update clocks latch out register flip flop 250 to clock in the data from the output of serial register flip flop 247 while outputting to a first data value input to multiplexer 246.
• top bsc output mode a signal to specify extest mode where a boundary scan cell drives I/O, and this signal is a first data input to a multiplexer 252.
• test_path_select a control signal input to a multiplexer 252 to select parallel input tmp to be output to the pad to enable design for testing (DFT) test path related to scan/dmled/PBIST, etc.
• DFT design for testing
• a four bit data register 254 associated with cell C x is a four bit data register 254, where its four bits are connected as follows:
• cell C x The operation of cell C x is as follows.
• cell C x may for one state output non-JTAG test or other data to the pad and for another state JTAG scan chain data may be output to the pad.
• bits in register 254 are programmed (or alternatively hard-coded) to select either the path from "parallel input tpm" or that of the latch out register 250 (i.e., by controlling multiplexer 246), so that the selected choice may then pass through multiplexer 242 to the pad.
• serial register 248 is part of the boundary scan chain in both states, making the entire boundary scan chain the same across different configurations, while the register 254 (or hard-coded) values ensure that a shifted in value in serial register 248 does not propagate to and affect the pads when not desired.
• the serial register 248 for each cell C x corresponding to such pads will get some shifted in value from a preceding cell in the chain, but that value does not propagate to the pad, so the pad continues to function as required for the test (i.e., by providing parallel input tpm instead to the pad).
• the serial register value in the cells corresponding to the first set of JTAG pads is allowed to propagate (via register 250 and multiplexers 246, 244, and 242) to each respective pad, thereby ensuring that they are controllable and testable through boundary scan testing.
• example embodiments provide improvements in boundary scan of ICs and printed circuit boards (PCBs).
• an example embodiment IC allows the sharing of pads, so that: in a first state, those pads may be used for JTAG testing, wherein during that state the pins bypass or otherwise are not pass-through connected to the configurable scan chain (although the TDI and TDO pads are serially connected for inputting and outputting data from the chain, rather than passing through data to functional circuitry 214); and, in a second state, the pads are used for non-JTAG signals that are pass-through connected to exclusive respective scan cells, and additional pads are used for JTAG testing of the dual-use pads during that second state.
• a set of IC pads may serve a second function beyond JTAG testing, such as for a functional interface such as an input/output for a universal asynchronous receiver/transmitter (UART) or as a serial peripheral interface (SPI).
• a functional interface such as an input/output for a universal asynchronous receiver/transmitter (UART) or as a serial peripheral interface (SPI).
• UART universal asynchronous receiver/transmitter
• SPI serial peripheral interface
• example embodiments may be less than 64 pads, less than 32 pads, or less than 16 pads. Such an approach reduces device cost as the number of pads can be reduced, or full JTAG testing for all pads is enabled in relatively low pad number devices. Thus, example embodiments permit 100% input/output test coverage on devices sharing JTAG pads for functional interfaces, as may be an important requirement for certain (e.g., safety, automotive) qualification. Also, board testing usually requires two different access protocols for devices with dual-use pads where one use is JTAG and for which scan chain JTAG testing is not permitted of the dual-use pads, because no corresponding boundary cells exist for such pads (such as in the example of FIG. 1), while example embodiments can eliminate the dual requirement.
• FIGS. 2a and 2b illustrate one example of switching configurations to create the configurable scan chain of boundary cells so as to bypass pass-through connectivity of selected cells for JTAG testing in respective different states, but various alternatives are possible. For example, while an example embodiment is shown to include 16 pads, various other numbers of pads may be implemented. Moreover, example embodiments may be created to include or exclude the optional TRST (test reset) JTAG signal.
• TRST test reset

Landscapes

• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Tests Of Electronic Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Test And Diagnosis Of Digital Computers (AREA)

Priority Applications (6)

Applications Claiming Priority (2)

Publications (1)

Family

ID=60022604

Family Applications (1)

Country Status (5)

Families Citing this family (7)

Citations (4)

Family Cites Families (53)

• 2016
  • 2016-04-29 US US15/143,454 patent/US9791505B1/en active Active
• 2017
  • 2017-05-01 CN CN202110742245.1A patent/CN113484719B/zh active Active
  • 2017-05-01 WO PCT/US2017/030359 patent/WO2017190123A1/en not_active Ceased
  • 2017-05-01 KR KR1020187034345A patent/KR102247968B1/ko active Active
  • 2017-05-01 CN CN201780031966.3A patent/CN109154633B/zh active Active
  • 2017-05-01 JP JP2018556862A patent/JP7004316B2/ja active Active
  • 2017-10-02 US US15/722,975 patent/US10274538B2/en active Active
• 2019
  • 2019-04-10 US US16/380,182 patent/US10983161B2/en active Active
• 2021
  • 2021-03-30 US US17/217,391 patent/US11821945B2/en active Active
  • 2021-12-22 JP JP2021207633A patent/JP7239913B2/ja active Active
• 2023
  • 2023-02-17 JP JP2023023870A patent/JP7505845B2/ja active Active

Patent Citations (4)

Also Published As

Similar Documents

Legal Events