CN109154633B - 全垫覆盖边界扫描 - Google Patents
全垫覆盖边界扫描 Download PDFInfo
- Publication number
- CN109154633B CN109154633B CN201780031966.3A CN201780031966A CN109154633B CN 109154633 B CN109154633 B CN 109154633B CN 201780031966 A CN201780031966 A CN 201780031966A CN 109154633 B CN109154633 B CN 109154633B
- Authority
- CN
- China
- Prior art keywords
- pads
- signals
- test
- state
- scan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110742245.1A CN113484719B (zh) | 2016-04-29 | 2017-05-01 | 全垫覆盖边界扫描 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/143,454 US9791505B1 (en) | 2016-04-29 | 2016-04-29 | Full pad coverage boundary scan |
| US15/143,454 | 2016-04-29 | ||
| PCT/US2017/030359 WO2017190123A1 (en) | 2016-04-29 | 2017-05-01 | Full pad coverage boundary scan |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110742245.1A Division CN113484719B (zh) | 2016-04-29 | 2017-05-01 | 全垫覆盖边界扫描 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109154633A CN109154633A (zh) | 2019-01-04 |
| CN109154633B true CN109154633B (zh) | 2021-08-24 |
Family
ID=60022604
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110742245.1A Active CN113484719B (zh) | 2016-04-29 | 2017-05-01 | 全垫覆盖边界扫描 |
| CN201780031966.3A Active CN109154633B (zh) | 2016-04-29 | 2017-05-01 | 全垫覆盖边界扫描 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110742245.1A Active CN113484719B (zh) | 2016-04-29 | 2017-05-01 | 全垫覆盖边界扫描 |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US9791505B1 (enExample) |
| JP (3) | JP7004316B2 (enExample) |
| KR (1) | KR102247968B1 (enExample) |
| CN (2) | CN113484719B (enExample) |
| WO (1) | WO2017190123A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113484719B (zh) * | 2016-04-29 | 2025-03-14 | 德州仪器公司 | 全垫覆盖边界扫描 |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7385651B2 (ja) * | 2018-08-31 | 2023-11-22 | エヌビディア コーポレーション | 自動車用途のための配置中にビルトイン・セルフテストを実行するためのテスト・システム |
| US11249134B1 (en) * | 2020-10-06 | 2022-02-15 | Qualcomm Incorporated | Power-collapsible boundary scan |
| CN112526327B (zh) * | 2020-10-28 | 2022-07-08 | 深圳市紫光同创电子有限公司 | 边界扫描测试方法及存储介质 |
| CN113589154B (zh) * | 2021-08-31 | 2025-07-08 | 成都海光集成电路设计有限公司 | 一种边界扫描电路 |
| CN113655376B (zh) * | 2021-09-13 | 2025-04-04 | 成都海光集成电路设计有限公司 | 一种扫描测试交换网络和扫描测试方法 |
| CN113938125B (zh) * | 2021-10-19 | 2023-02-24 | 浙江大学 | 多通道可配置可测试与修调的数字信号隔离器 |
Citations (8)
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| US6351836B1 (en) * | 1998-06-08 | 2002-02-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with boundary scanning circuit |
| JP2003228999A (ja) * | 2002-02-01 | 2003-08-15 | Rohm Co Ltd | 半導体記憶装置 |
| TW558640B (en) * | 2002-02-06 | 2003-10-21 | Guo-Jan Peng | Debugging and positioning method of chip and equipment thereof |
| US6711708B1 (en) * | 1999-03-23 | 2004-03-23 | Mitsubishi Denki Kabushiki Kaisha | Boundary-scan test method and device |
| CN1748154A (zh) * | 2003-02-10 | 2006-03-15 | 皇家飞利浦电子股份有限公司 | 集成电路的测试 |
| US7036061B2 (en) * | 2001-08-28 | 2006-04-25 | Intel Corporation | Structural input levels testing using on-die levels generators |
| CN101228451A (zh) * | 2005-07-22 | 2008-07-23 | Nxp股份有限公司 | 可测试集成电路,系统级封装和测试指令集 |
| US7702983B2 (en) * | 2006-05-04 | 2010-04-20 | Stmicroelectronics S.R.L. | Scan compression architecture for a design for testability compiler used in system-on-chip software design tools |
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| JP2561164B2 (ja) * | 1990-02-26 | 1996-12-04 | 三菱電機株式会社 | 半導体集積回路 |
| JP2627464B2 (ja) * | 1990-03-29 | 1997-07-09 | 三菱電機株式会社 | 集積回路装置 |
| US5513188A (en) * | 1991-09-10 | 1996-04-30 | Hewlett-Packard Company | Enhanced interconnect testing through utilization of board topology data |
| JP2741119B2 (ja) * | 1991-09-17 | 1998-04-15 | 三菱電機株式会社 | バイパススキャンパスおよびそれを用いた集積回路装置 |
| US5231314A (en) * | 1992-03-02 | 1993-07-27 | National Semiconductor Corporation | Programmable timing circuit for integrated circuit device with test access port |
| US5270642A (en) * | 1992-05-15 | 1993-12-14 | Hewlett-Packard Company | Partitioned boundary-scan testing for the reduction of testing-induced damage |
| US5471481A (en) * | 1992-05-18 | 1995-11-28 | Sony Corporation | Testing method for electronic apparatus |
| US5404359A (en) * | 1992-06-29 | 1995-04-04 | Tandem Computers Incorporated | Fail safe, fault tolerant circuit for manufacturing test logic on application specific integrated circuits |
| US5477545A (en) * | 1993-02-09 | 1995-12-19 | Lsi Logic Corporation | Method and apparatus for testing of core-cell based integrated circuits |
| JPH0862294A (ja) * | 1994-08-25 | 1996-03-08 | Mitsubishi Electric Corp | 半導体装置及び半導体装置のテスト方法 |
| US5592493A (en) * | 1994-09-13 | 1997-01-07 | Motorola Inc. | Serial scan chain architecture for a data processing system and method of operation |
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| US5804996A (en) * | 1997-02-13 | 1998-09-08 | Ramtron International Corporation | Low-power non-resetable test mode circuit |
| JP3835884B2 (ja) * | 1997-04-30 | 2006-10-18 | 株式会社 沖マイクロデザイン | 半導体集積回路の入力回路 |
| KR20010042264A (ko) * | 1998-04-03 | 2001-05-25 | 가나이 쓰토무 | 반도체장치 |
| JP3866444B2 (ja) | 1998-04-22 | 2007-01-10 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置及びその内部信号モニタ方法 |
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| JP4480238B2 (ja) | 2000-07-18 | 2010-06-16 | Okiセミコンダクタ株式会社 | 半導体装置 |
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-
2016
- 2016-04-29 US US15/143,454 patent/US9791505B1/en active Active
-
2017
- 2017-05-01 CN CN202110742245.1A patent/CN113484719B/zh active Active
- 2017-05-01 JP JP2018556862A patent/JP7004316B2/ja active Active
- 2017-05-01 KR KR1020187034345A patent/KR102247968B1/ko active Active
- 2017-05-01 CN CN201780031966.3A patent/CN109154633B/zh active Active
- 2017-05-01 WO PCT/US2017/030359 patent/WO2017190123A1/en not_active Ceased
- 2017-10-02 US US15/722,975 patent/US10274538B2/en active Active
-
2019
- 2019-04-10 US US16/380,182 patent/US10983161B2/en active Active
-
2021
- 2021-03-30 US US17/217,391 patent/US11821945B2/en active Active
- 2021-12-22 JP JP2021207633A patent/JP7239913B2/ja active Active
-
2023
- 2023-02-17 JP JP2023023870A patent/JP7505845B2/ja active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6351836B1 (en) * | 1998-06-08 | 2002-02-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with boundary scanning circuit |
| US6711708B1 (en) * | 1999-03-23 | 2004-03-23 | Mitsubishi Denki Kabushiki Kaisha | Boundary-scan test method and device |
| US7036061B2 (en) * | 2001-08-28 | 2006-04-25 | Intel Corporation | Structural input levels testing using on-die levels generators |
| JP2003228999A (ja) * | 2002-02-01 | 2003-08-15 | Rohm Co Ltd | 半導体記憶装置 |
| TW558640B (en) * | 2002-02-06 | 2003-10-21 | Guo-Jan Peng | Debugging and positioning method of chip and equipment thereof |
| CN1748154A (zh) * | 2003-02-10 | 2006-03-15 | 皇家飞利浦电子股份有限公司 | 集成电路的测试 |
| CN101228451A (zh) * | 2005-07-22 | 2008-07-23 | Nxp股份有限公司 | 可测试集成电路,系统级封装和测试指令集 |
| US7702983B2 (en) * | 2006-05-04 | 2010-04-20 | Stmicroelectronics S.R.L. | Scan compression architecture for a design for testability compiler used in system-on-chip software design tools |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113484719B (zh) * | 2016-04-29 | 2025-03-14 | 德州仪器公司 | 全垫覆盖边界扫描 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20190235020A1 (en) | 2019-08-01 |
| JP2022043194A (ja) | 2022-03-15 |
| JP2019515282A (ja) | 2019-06-06 |
| KR102247968B1 (ko) | 2021-05-03 |
| WO2017190123A1 (en) | 2017-11-02 |
| JP7239913B2 (ja) | 2023-03-15 |
| CN113484719A (zh) | 2021-10-08 |
| US20210215757A1 (en) | 2021-07-15 |
| JP2023063323A (ja) | 2023-05-09 |
| CN109154633A (zh) | 2019-01-04 |
| CN113484719B (zh) | 2025-03-14 |
| US20180045778A1 (en) | 2018-02-15 |
| JP7004316B2 (ja) | 2022-02-04 |
| KR20180133926A (ko) | 2018-12-17 |
| US10274538B2 (en) | 2019-04-30 |
| US10983161B2 (en) | 2021-04-20 |
| JP7505845B2 (ja) | 2024-06-25 |
| US9791505B1 (en) | 2017-10-17 |
| US11821945B2 (en) | 2023-11-21 |
| US20170315174A1 (en) | 2017-11-02 |
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