JP2018148029A - 半導体エピタキシャルウェハ、半導体素子、および半導体素子の製造方法 - Google Patents
半導体エピタキシャルウェハ、半導体素子、および半導体素子の製造方法 Download PDFInfo
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Abstract
Description
以下、図面を参照しながら、炭化珪素エピタキシャルウェハおよび炭化珪素半導体素子(MISFET)を例に、半導体エピタキシャルウェハおよび半導体素子の第1の実施形態を説明する。ここでは、第1導電型としてp型、第2導電型としてn型の導電型を有するMISFETを例に説明するが、本実施形態の炭化珪素半導体素子は、第1導電型としてn型、第2導電型としてp型の導電型を有するMISFETであってもよい。
本実施形態では、炭化珪素ウェハ301面内、あるいは、炭化珪素半導体素子200における炭化珪素基板101面内において、チャネル層106の厚さ分布とチャネル層106の第1導電型の不純物の濃度分布とが負の相関を有している。「負の相関」とは、例えば、炭化珪素ウェハ301または炭化珪素基板101に平行な面内において、チャネル層106の厚さの異なる2点a、bをとり、点a、bのチャネル層106の厚さをそれぞれDa、Db、チャネル層106の第1導電型不純物の濃度をそれぞれCa、Cbとすると、Da>DbのときCa<Cbであるか、または、Da<DbのときCa>Cbである場合を指す。
チャネル層106は、単一のn型不純物層またはp型不純物層であってもよい。チャネル層106が単一の不純物層からなる場合、チャネル層106の第1導電型不純物の濃度は、例えば1×1018以上1×1019cm−3以下、厚さは10nm以上100nm以下であってもよい。
チャネル層106の厚さ分布と不純物濃度分布との相関関係(負の相関)に加えて、あるいはそれに代わって、炭化珪素ウェハ301面内、あるいは、炭化珪素半導体素子200における炭化珪素基板101面内において、チャネル層106の厚さ分布とゲート絶縁膜107の厚さ分布とが正の相関を有していてもよい。「正の相関」とは、例えば、炭化珪素ウェハ301または炭化珪素基板101に平行な面内において、チャネル層106の厚さの異なる2点a、bをとり、点a、bにおけるチャネル層106の厚さをそれぞれDa、Db、ゲート絶縁膜107の厚さをそれぞれTa、Tbとすると、Da>DbのときTa>Tbであるか、または、Da<DbのときTa<Tbである場合を指す。
本発明者は、MISFETの各工程で生じるばらつき量のゲート閾値電圧Vthへの影響を試算したので、以下に説明する。
次に、図面を参照しながら、本実施形態の炭化珪素半導体素子200の製造方法を説明する。
実施例および比較例のMISFETを試作し、炭化珪素ウェハ301面内における素子特性のばらつきを測定したので、その方法および結果を説明する。
101 :炭化珪素基板
102 :ドリフト領域
103 :ボディ領域
104 :ソース領域
105 :コンタクト領域
106 :チャネル層
107 :ゲート絶縁膜
108 :ゲート電極
109 :ソース電極
110 :炭化珪素エピタキシャル層
111 :層間絶縁層
112 :ソース配線
114 :ドレイン電極
120 :JFET領域
160 :高濃度不純物層
161 :ボトム層
162 :キャップ層
200 :炭化珪素半導体素子
201 :ソースパッド
202 :ゲートパッド
300 :炭化珪素エピタキシャルウェハ
301 :炭化珪素ウェハ
Rc :素子領域
Ru :ユニットセル形成領域
Claims (20)
- 半導体ウェハと、前記半導体ウェハ上に配置された第1導電型の半導体層とを備える半導体エピタキシャルウェハであって、
複数の素子領域を有し、
前記複数の素子領域のそれぞれは、
前記半導体層に接する第2導電型のボディ領域と、
前記ボディ領域に接する第1導電型のソース領域と、
前記半導体層上でかつ前記ボディ領域の少なくとも一部に接して配置された、半導体からなるチャネル層と
を含み、
前記チャネル層は、1×1018/cm3以上1×1019/cm3以下の濃度で第1導電型の不純物を含み、かつ、前記チャネル層の厚さは10nm以上100nm以下であり、
前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布と前記チャネル層の第1導電型の不純物の濃度分布とが負の相関を有する半導体エピタキシャルウェハ。 - 前記半導体ウェハに平行な面内の2点a、bにおける前記チャネル層の厚さをそれぞれDa、Dbとし、前記チャネル層の第1導電型の不純物の濃度をCa、Cbとすると、Da>DbのときCa<Cbであるか、または、Da<DbのときCa>Cbである、請求項1に記載の半導体エピタキシャルウェハ。
- 前記複数の素子領域のそれぞれは、
前記チャネル層上に配置されたゲート絶縁膜と、
前記ゲート絶縁膜上に配置されたゲート電極と
をさらに含み、
前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布と前記ゲート絶縁膜の厚さ分布とが正の相関を有する、請求項1または2に記載の半導体エピタキシャルウェハ。 - 前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布における最大値と最小値との差は、2nm以上20nmであり、前記チャネル層の第1導電型の不純物の濃度分布における最大値と最小値との差は、2×1017/cm3以上2×1018/cm3以下である、請求項1から3のいずれかに記載の半導体エピタキシャルウェハ。
- 前記チャネル層の第1導電型の不純物濃度は、前記半導体ウェハの中央部で周縁部よりも低く、前記チャネル層の厚さは、前記半導体ウェハの中央部で周縁部よりも高い、請求項1から4のいずれかに記載の半導体エピタキシャルウェハ。
- 半導体ウェハと、前記半導体ウェハ上に配置された第1導電型の半導体層とを備える半導体エピタキシャルウェハであって、
複数の素子領域を有し、
前記複数の素子領域のそれぞれは、
前記半導体層に接する第2導電型のボディ領域と、
前記ボディ領域に接する第1導電型のソース領域と、
前記半導体層上でかつ前記ボディ領域の少なくとも一部に接して配置された、半導体からなるチャネル層と、
前記チャネル層上に配置されたゲート絶縁膜と、
前記ゲート絶縁膜上に配置されたゲート電極と
を含み、
前記チャネル層は、1×1018/cm3以上1×1019/cm3以下の濃度で第1導電型の不純物を含み、かつ、前記チャネル層の厚さは10nm以上100nm以下であり、
前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布と前記ゲート絶縁膜の厚さ分布とが正の相関を有する、半導体エピタキシャルウェハ。 - 前記半導体ウェハに平行な面内の2点a、bにおける前記チャネル層の厚さをそれぞれDa、Dbとし、前記ゲート絶縁膜の厚さをTa、Tbとすると、Da>DbのときTa>Tbであるか、または、Da<DbのときTa<Tbである、請求項6に記載の半導体エピタキシャルウェハ。
- 前記チャネル層および前記ゲート絶縁膜は、いずれも、前記半導体ウェハの中央部で周縁部よりも厚い、請求項6または7に記載の半導体エピタキシャルウェハ。
- 前記ゲート絶縁膜は、熱酸化膜である、請求項3および6から8のいずれかに記載の半導体エピタキシャルウェハ。
- 前記半導体ウェハは炭化珪素ウェハであり、前記半導体層は炭化珪素半導体層であり、前記チャネル層は炭化珪素半導体からなる、請求項1から9のいずれかに記載の半導体エピタキシャルウェハ。
- 半導体基板と、
前記半導体基板上に配置された第1導電型の半導体層と、
前記半導体層に接する第2導電型のボディ領域と、
前記ボディ領域に接する第1導電型のソース領域と、
前記半導体層上でかつ前記ボディ領域の少なくとも一部に接して配置された、半導体からなるチャネル層と
を含み、
前記チャネル層は、1×1018/cm3以上1×1019/cm3以下の濃度で第1導電型の不純物を含み、かつ、前記チャネル層の厚さは10nm以上100nm以下であり、
前記半導体基板に平行な面内における、前記チャネル層の厚さ分布と前記チャネル層の第1導電型の不純物の濃度分布とが負の相関を有する半導体素子。 - 前記チャネル層上に配置されたゲート絶縁膜と、
前記ゲート絶縁膜上に配置されたゲート電極と、
をさらに含み、
前記半導体基板に平行な面内における、前記チャネル層の厚さ分布と前記ゲート絶縁膜の厚さ分布とが正の相関を有する、請求項11に記載の半導体素子。 - 前記半導体基板に平行な面内における、前記チャネル層の厚さ分布における最大値と最小値との差は、1nm以上5nm以下であり、前記チャネル層の第1導電型の不純物の濃度分布における最大値と最小値との差は、1×1017/cm3以上1×1018/cm3以下である、請求項11または12に記載の半導体素子。
- 前記半導体基板に平行な面内における、前記チャネル層の厚さ分布における最大値と最小値との差は、1nm以上2nm以下であり、前記チャネル層の第1導電型の不純物の濃度分布における最大値と最小値との差は、1×1017/cm3以上2×1017/cm3以下である、請求項13に記載の半導体素子。
- 半導体基板と、
前記半導体基板上に配置された第1導電型の半導体層と
前記半導体層に接する第2導電型のボディ領域と、
前記ボディ領域に接する第1導電型のソース領域と、
前記半導体層上でかつ前記ボディ領域の少なくとも一部に接して配置された、半導体からなるチャネル層と、
前記チャネル層上に配置されたゲート絶縁膜と、
前記ゲート絶縁膜上に配置されたゲート電極と
を含み、
前記チャネル層は、1×1018/cm3以上1×1019/cm3以下の濃度で第1導電型の不純物を含み、かつ、前記チャネル層の厚さは10nm以上100nm以下であり、
前記半導体基板に平行な面内における、前記チャネル層の厚さ分布と前記ゲート絶縁膜の厚さ分布とが正の相関を有する、半導体素子。 - 前記半導体基板は炭化珪素基板であり、前記半導体層は炭化珪素半導体層であり、前記チャネル層は炭化珪素半導体からなる、請求項11から15のいずれかに記載の半導体素子。
- (A)半導体ウェハと、前記半導体ウェハの主面上に配置され、第1導電型の不純物を含む半導体層とを備えた半導体エピタキシャルウェハであって、複数の素子領域を有し、前記複数の素子領域のそれぞれは、前記半導体層に接する第2導電型のボディ領域と、前記ボディ領域に接する第1導電型のソース領域とを含む、半導体エピタキシャルウェハを用意する工程と、
(B)前記半導体層の表面に半導体をエピタキシャル成長させることによって、前記ボディ領域の少なくとも一部に接するチャネル層を形成する工程と
を包含し、
前記チャネル層は、1×1018/cm3以上1×1019/cm3以下の濃度で第1導電型の不純物を含み、かつ、前記チャネル層の厚さは10nm以上100nm以下であり、
前記工程(B)において、前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布と前記チャネル層の第1導電型の不純物の濃度分布とが負の相関を有するように、エピタキシャル成長させる条件を制御する半導体素子の製造方法。 - (C)前記チャネル層上にゲート絶縁膜を形成する工程をさらに包含し、
前記工程(B)および前記工程(C)において、前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布と前記ゲート絶縁膜の厚さ分布とが正の相関を有するように、前記エピタキシャル成長させる条件および前記ゲート絶縁膜の形成条件を制御する請求項17に記載の半導体素子の製造方法。 - (A)半導体ウェハと、前記半導体ウェハの主面上に配置され、第1導電型の不純物を含む半導体層とを備えた半導体エピタキシャルウェハであって、複数の素子領域を有し、前記複数の素子領域のそれぞれは、前記半導体層に接する第2導電型のボディ領域と、前記ボディ領域に接する第1導電型のソース領域とを含む、半導体エピタキシャルウェハを用意する工程と、
(B)前記半導体層の表面に半導体をエピタキシャル成長させることによって、前記ボディ領域の少なくとも一部に接するチャネル層を形成する工程と、
(C)前記チャネル層上にゲート絶縁膜を形成する工程と
を包含し、
前記チャネル層は、1×1018/cm3以上1×1019/cm3以下の濃度で第1導電型の不純物を含み、かつ、前記チャネル層の厚さは10nm以上100nm以下であり、
前記工程(B)および前記工程(C)において、前記半導体ウェハに平行な面内における、前記チャネル層の厚さ分布と前記ゲート絶縁膜の厚さ分布とが正の相関を有するように、エピタキシャル成長させる条件および前記ゲート絶縁膜の形成条件を制御する半導体素子の製造方法。 - 前記半導体ウェハは炭化珪素ウェハであり、前記半導体層は炭化珪素半導体層であり、前記チャネル層は炭化珪素半導体からなる、請求項17から19のいずれかに記載の半導体素子の製造方法。
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