JP2017228719A5 - - Google Patents

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Publication number
JP2017228719A5
JP2017228719A5 JP2016125463A JP2016125463A JP2017228719A5 JP 2017228719 A5 JP2017228719 A5 JP 2017228719A5 JP 2016125463 A JP2016125463 A JP 2016125463A JP 2016125463 A JP2016125463 A JP 2016125463A JP 2017228719 A5 JP2017228719 A5 JP 2017228719A5
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JP
Japan
Prior art keywords
metal film
layer
metal
recess
insulating layer
Prior art date
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JP2016125463A
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English (en)
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JP2017228719A (ja
JP6615701B2 (ja
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Priority to JP2016125463A priority Critical patent/JP6615701B2/ja
Priority claimed from JP2016125463A external-priority patent/JP6615701B2/ja
Priority to US15/627,542 priority patent/US10396024B2/en
Publication of JP2017228719A publication Critical patent/JP2017228719A/ja
Publication of JP2017228719A5 publication Critical patent/JP2017228719A5/ja
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Publication of JP6615701B2 publication Critical patent/JP6615701B2/ja
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Description

１０ 配線基板
１５ 配線層
１６ 絶縁層（第１絶縁層）
１６Ｘ 貫通孔（第１貫通孔）
１６Ｙ 凹部（第２凹部）
１７ 絶縁層（第２絶縁層）
２３ ビア配線
２５ バンプ
２６ 凹部（第１凹部）
３０ 金属膜（第２金属膜）
３０Ｒ 粗化面
３１ 金属膜（第１金属膜）
３３ 金属層（第１金属層）
５０ 半導体装置
６０ 半導体素子（電子部品）
１００ 支持基板
１０４ 金属膜（第３金属膜）
１０５ 金属膜（第４金属膜）
１０７ 金属層（第２金属層）
１０８，１０８Ａ，１０８Ｂ 犠牲パターン
JP2016125463A 2016-06-24 2016-06-24 配線基板、半導体装置及び配線基板の製造方法 Active JP6615701B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016125463A JP6615701B2 (ja) 2016-06-24 2016-06-24 配線基板、半導体装置及び配線基板の製造方法
US15/627,542 US10396024B2 (en) 2016-06-24 2017-06-20 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016125463A JP6615701B2 (ja) 2016-06-24 2016-06-24 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2017228719A JP2017228719A (ja) 2017-12-28
JP2017228719A5 true JP2017228719A5 (ja) 2019-02-07
JP6615701B2 JP6615701B2 (ja) 2019-12-04

Family

ID=60677898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016125463A Active JP6615701B2 (ja) 2016-06-24 2016-06-24 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

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US (1) US10396024B2 (ja)
JP (1) JP6615701B2 (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10297521B2 (en) * 2015-04-27 2019-05-21 Kyocera Corporation Circuit substrate, and electronic device including same
US10276528B2 (en) * 2017-07-18 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor device and manufacturing method thereof
JP7202784B2 (ja) * 2018-04-27 2023-01-12 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US10573583B2 (en) * 2018-06-20 2020-02-25 Texas Instruments Incorporated Semiconductor device package with grooved substrate
KR102145203B1 (ko) * 2018-07-19 2020-08-18 삼성전자주식회사 팬-아웃 반도체 패키지
JP7240909B2 (ja) * 2019-03-13 2023-03-16 新光電気工業株式会社 配線基板及びその製造方法
WO2020215225A1 (zh) * 2019-04-23 2020-10-29 庆鼎精密电子（淮安）有限公司 电路板及其制作方法
US10950531B2 (en) * 2019-05-30 2021-03-16 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
CN113517209A (zh) * 2020-04-10 2021-10-19 长鑫存储技术有限公司 半导体结构及其形成方法
KR20220086321A (ko) * 2020-12-16 2022-06-23 삼성전기주식회사 인쇄회로기판 및 전자부품 패키지

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003109987A (ja) * 2001-10-02 2003-04-11 Toshiba Corp フリップチップ実装基板および半導体装置
US7190078B2 (en) * 2004-12-27 2007-03-13 Khandekar Viren V Interlocking via for package via integrity
US20060178007A1 (en) * 2005-02-04 2006-08-10 Hiroki Nakamura Method of forming copper wiring layer
TWI390692B (zh) * 2009-06-23 2013-03-21 Unimicron Technology Corp 封裝基板與其製法暨基材
JP5355380B2 (ja) 2009-12-25 2013-11-27 新光電気工業株式会社 多層配線基板
JP5502624B2 (ja) * 2010-07-08 2014-05-28 新光電気工業株式会社 配線基板の製造方法及び配線基板
KR101677507B1 (ko) * 2010-09-07 2016-11-21 삼성전자주식회사 반도체 장치의 제조 방법
JP2013211497A (ja) * 2012-03-30 2013-10-10 Keihin Corp 部品接合構造
CN103985683B (zh) * 2013-02-08 2017-04-12 精材科技股份有限公司 晶片封装体
JP6201663B2 (ja) * 2013-11-13 2017-09-27 大日本印刷株式会社 貫通電極基板の製造方法、貫通電極基板、および半導体装置
US9553059B2 (en) * 2013-12-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Backside redistribution layer (RDL) structure
JP2016004888A (ja) * 2014-06-17 2016-01-12 イビデン株式会社 プリント配線板及びプリント配線板の製造方法

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