JP2010028601A5 - - Google Patents

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Publication number
JP2010028601A5
JP2010028601A5 JP2008189358A JP2008189358A JP2010028601A5 JP 2010028601 A5 JP2010028601 A5 JP 2010028601A5 JP 2008189358 A JP2008189358 A JP 2008189358A JP 2008189358 A JP2008189358 A JP 2008189358A JP 2010028601 A5 JP2010028601 A5 JP 2010028601A5
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JP
Japan
Prior art keywords
ceramic substrate
circuit pattern
connection pads
view
circuit
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JP2008189358A
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English (en)
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JP2010028601A (ja
JP5183340B2 (ja
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Priority to JP2008189358A priority Critical patent/JP5183340B2/ja
Priority claimed from JP2008189358A external-priority patent/JP5183340B2/ja
Publication of JP2010028601A publication Critical patent/JP2010028601A/ja
Publication of JP2010028601A5 publication Critical patent/JP2010028601A5/ja
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Publication of JP5183340B2 publication Critical patent/JP5183340B2/ja
Expired - Fee Related legal-status Critical Current
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Description

図5は、本発明にかかる発振器の背面に設ける面実装端子のパターン例を説明する図であり、図5(a)はセラミック基板の背面図、(b)は同じくセラミック基板の断面図である。図5において、符号23はセラミック基板1に形成されて図1で説明したICチップ5のバンプ6を接続する接続パッドを有する回路パターンである。なお、この回路パターンに設ける上記の接続パッドや関連する回路パターンの表記は省略し、回路パターンを形成する導体として一括図示した。
JP2008189358A 2008-07-23 2008-07-23 表面実装型の発振器およびこの発振器を搭載した電子機器 Expired - Fee Related JP5183340B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008189358A JP5183340B2 (ja) 2008-07-23 2008-07-23 表面実装型の発振器およびこの発振器を搭載した電子機器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008189358A JP5183340B2 (ja) 2008-07-23 2008-07-23 表面実装型の発振器およびこの発振器を搭載した電子機器

Publications (3)

Publication Number Publication Date
JP2010028601A JP2010028601A (ja) 2010-02-04
JP2010028601A5 true JP2010028601A5 (ja) 2012-07-12
JP5183340B2 JP5183340B2 (ja) 2013-04-17

Family

ID=41733978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008189358A Expired - Fee Related JP5183340B2 (ja) 2008-07-23 2008-07-23 表面実装型の発振器およびこの発振器を搭載した電子機器

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JP (1) JP5183340B2 (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
KR101588723B1 (ko) 2007-07-31 2016-01-26 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151627A (ja) * 2000-11-09 2002-05-24 Hitachi Ltd 半導体装置、その製造方法および実装方法
JP2006019455A (ja) * 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
JP2007067173A (ja) * 2005-08-31 2007-03-15 Kyocera Kinseki Corp 電子部品
JP2008072321A (ja) * 2006-09-13 2008-03-27 Tdk Corp 電子部品
JP4328347B2 (ja) * 2006-11-10 2009-09-09 ホシデン株式会社 マイクロホン及びその実装構造

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