JP2015511072A - メモリセル、係るメモリセルを含む半導体デバイス構造、システム、および製作の方法 - Google Patents
メモリセル、係るメモリセルを含む半導体デバイス構造、システム、および製作の方法 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3286—Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/08—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers
- H01F10/10—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition
- H01F10/18—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition being compounds
- H01F10/193—Magnetic semiconductor compounds
- H01F10/1936—Half-metallic, e.g. epitaxial CrO2 or NiMnSb films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/329—Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
Description
本願は、2012年3月22日に出願された「Memory Cells,Semiconductor Device Structures,Systems Including Such Cells,and Methods of Fabrication」を発明の名称とする米国特許出願整理番号第13/427,339号の出願日の利益を主張する。
Claims (20)
- 垂直の磁化方向を生じさせる歪みを示すフリー領域を含む磁気セルコアを含む、少なくとも1つのメモリセル、
を含む半導体デバイス。 - 前記少なくとも1つのメモリセルは、前記磁気セルコアの外部に位置し且つ前記磁気セルコアに応力を印加する少なくとも1つのストレッサー構造をさらに含む、請求項1に記載の半導体デバイス。
- 前記少なくとも1つのストレッサー構造は横方向応力および垂直応力のうちの少なくとも1つを前記フリー領域に対して作用させる、請求項2に記載の半導体デバイス。
- 前記少なくとも1つのストレッサー構造は圧縮応力および引張応力のうちの少なくとも1つを前記フリー領域に対して作用させる、請求項2に記載の半導体デバイス。
- 前記少なくとも1つのストレッサー構造は前記磁気セルコアを横方向に包囲する、請求項4に記載の半導体デバイス。
- 前記磁気セルコアは横方向に前記少なくとも1つのストレッサー構造の少なくとも2つのセグメントの間に配置される、請求項2に記載の半導体デバイス。
- 前記少なくとも1つのストレッサー構造は横方向圧縮応力を前記フリー領域に印加する、請求項6に記載の半導体デバイス。
- 前記磁気セルコアは垂直に前記少なくとも1つのストレッサー構造の少なくとも2つのセグメントの間に配置される、請求項2に記載の半導体デバイス。
- 前記少なくとも1つのストレッサー構造は垂直引張応力を前記フリー領域に印加する、請求項8に記載の半導体デバイス。
- 前記少なくとも1つのストレッサー構造は複数のストレッサー物質を含む、請求項2に記載の半導体デバイス。
- 前記フリー領域は磁歪効果を示す物質を含む、請求項1に記載の半導体デバイス。
- 前記フリー領域はホイスラー合金を含む、請求項1に記載の半導体デバイス。
- 前記磁気セルコアは垂直の磁化方向を示す固定領域をさらに含む、請求項1に記載の半導体デバイス。
- 前記少なくとも1つのメモリセルは、
複数のメモリセルのうちの各メモリセルの前記磁気セルコアに動作可能に連通するワード線、および
前記複数のメモリセルのうちの各メモリセルの前記磁気セルコアに動作可能に連通するビット線、
を含むアレイ内に複数のメモリセルを含み、
前記複数のメモリセルのうちの各メモリセルの前記フリー領域の前記垂直の磁化方向は、前記磁気セルコアに動作可能に連通する前記ワード線および前記ビット線のうちの1つに向けられる、
請求項1〜請求項13のうちのいずれか1つに記載の半導体デバイス。 - メモリセルを形成する方法であって、
セルコアを形成することと、
前記セルコアに応力を印加して、前記セルコア内の物質により示される磁化方向に影響を及ぼすことと
を含む方法。 - セルコアを形成することは、
固定領域を形成することと、
前記固定領域の上方に非磁性領域を形成することと、
前記非磁性領域の上方にフリー領域を形成することと
を含む、請求項15に記載の方法。 - 前記セルコアの外部に位置する少なくとも1つのストレッサー構造を用いて前記セルコアに前記応力を印加することをさらに含む、請求項15に記載の方法。
- 前記少なくとも1つのストレッサー構造を前記セルコア上に形成することをさらに含み、前記少なくとも1つのストレッサー構造は、前記セルコアの隣接物質の熱膨張係数とは異なる熱膨張係数を有するストレッサー物質を含む、請求項17に記載の方法。
- 前記少なくとも1つのストレッサー構造の形成後、前記少なくとも1つのストレッサー構造の温度を低下させ、それにより前記隣接物質に応力を印加し、前記セルコア内の前記フリー領域の磁化方向に影響を及ぼすことをさらに含む、請求項18に記載の方法。
- 前記セルコアと前記少なくとも1つのストレッサー構造との間に絶縁性物質を配置することをさらに含む、請求項17に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/427,339 US9007818B2 (en) | 2012-03-22 | 2012-03-22 | Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication |
US13/427,339 | 2012-03-22 | ||
PCT/US2013/033344 WO2013142713A1 (en) | 2012-03-22 | 2013-03-21 | Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication |
Publications (2)
Publication Number | Publication Date |
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JP2015511072A true JP2015511072A (ja) | 2015-04-13 |
JP5892575B2 JP5892575B2 (ja) | 2016-03-23 |
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JP2015501917A Active JP5892575B2 (ja) | 2012-03-22 | 2013-03-21 | メモリセル、係るメモリセルを含む半導体デバイス構造、システム、および製作の方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US9007818B2 (ja) |
EP (1) | EP2828858B1 (ja) |
JP (1) | JP5892575B2 (ja) |
KR (1) | KR101689944B1 (ja) |
CN (1) | CN104321819B (ja) |
TW (1) | TWI523289B (ja) |
WO (1) | WO2013142713A1 (ja) |
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