JP2015133452A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP2015133452A JP2015133452A JP2014005373A JP2014005373A JP2015133452A JP 2015133452 A JP2015133452 A JP 2015133452A JP 2014005373 A JP2014005373 A JP 2014005373A JP 2014005373 A JP2014005373 A JP 2014005373A JP 2015133452 A JP2015133452 A JP 2015133452A
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Abstract
【解決手段】アルミニウムを含有する最上層の配線M4上の保護膜PROに、配線M4のパッド領域PD1を露出する開口部OA1を形成し、露出した配線M4の表面に、窒化アルミニウムを形成する。そして、この配線M4を有する半導体基板の裏面には、窒化シリコン膜が形成されている。このように、パッド領域PD1上に窒化アルミニウム膜M4eを設けることで、半導体基板の裏面の窒化シリコン膜に起因してパッド領域PD1上に生じる異物を防止することができる。特に、パッド領域PD1の形成工程の後において、検査工程やボンディング工程までに時間を要する場合があっても、パッド領域PD1において異物の生成反応を防止でき、半導体装置の特性を向上させることができる。
【選択図】図1
Description
以下、図面を参照しながら本実施の形態の半導体装置の構造について説明する。
図1は、本実施の形態の半導体装置の構成を示す断面図である。本実施の形態の半導体装置は、nチャネル型MISFET(NT)およびpチャネル型MISFET(PT)を有する。
2Al=2Al3 ++6e− …(化学式1)
6NH3+6H2O=6NH4 ++6OH− …(化学式2)
2Al3 ++6HO−=2Al(OH)3↓ …(化学式3)
6NH4 ++6e−=6NH3+3H2↑ …(化学式4)
このような、異物(Al(OH)3)が生じた場合は、パッド領域PD1上に導電性部材(バンプ電極、ボンディングワイヤ)を精度よく形成することができず、不良となってしまう。
次いで、図3〜図26を参照しながら、本実施の形態の半導体装置の製造方法を説明する。図3〜図26(図5、図6除く)は、本実施の形態の半導体装置の製造工程を示す断面図である。
上記製造工程においては、開口部OA1を形成した後、アルミニウム膜M4bのパッド領域PD1の窒化処理を行ったが、アルミニウム膜M4bのパッド領域PD1に不動態化処理(酸化処理)を行った後、窒化処理を行ってもよい。なお、アルミニウム膜M4bのパッド領域PD1上の構成以外は実施の形態1と同様であるため、その詳細な説明を省略する。
図29は、NH3プラズマ処理の有無と腐食発生数との関係を示すグラフである。横軸は、ウエハ番号であり、縦軸は、腐食発生数[個]である。半導体基板の裏面に窒化シリコン膜が形成され、かつ、パッド領域PD1が露出した状態で、8日間放置(保存)した24枚のウエハ(半導体基板)と、12日間放置(保存)した24枚のウエハ(半導体基板)について外観検査試験を行った。
実施の形態1においては、パッド領域PD1上に、導電性部材よりなる突起電極(バンプ電極)BPを形成したが(図26参照)、パッド領域PD1上に再配線を設け、この再配線上に、導電性部材よりなる突起電極BPを設けてもよい。
100a チャンバー
100b ガス導入孔
100c ステージ
BP 突起電極
GE ゲート電極
GI ゲート絶縁膜
IL 層間絶縁膜
IL1 層間絶縁膜
IL1a 窒化シリコン膜
IL1b 酸化シリコン膜
IL2 層間絶縁膜
IL3 層間絶縁膜
IL4 層間絶縁膜
IL5 層間絶縁膜
IL5a 窒化シリコン膜
IL5b 酸化シリコン膜
M 金属膜
M1 配線
M2 配線
M3 配線
M4 配線
M4a チタン/窒化チタン膜
M4b アルミニウム膜
M4c チタン膜
M4d 酸化アルミニウム膜
M4e 窒化アルミニウム膜
M4f 酸化アルミニウム
MN マスク膜
MP マスク膜
NM n−型半導体領域
NP n+型半導体領域
NT nチャネル型MISFET
NW n型ウエル
OA1 開口部
OA2 開口部
P1 プラグ
P2 プラグ
P3 プラグ
P4 プラグ
PA 異物
PD1 パッド領域
PD2 パッド領域
PI 保護膜
PIN 領域(ピンホール)
PM p−型半導体領域
PP p+型半導体領域
PRO 保護膜
PROa 窒化シリコン膜
PROb 酸化シリコン膜
PT pチャネル型MISFET
PW p型ウエル
RW 再配線
RWa アルミニウム膜
RWb 窒化アルミニウム膜
S 半導体基板
SIL 金属シリサイド膜
SM シリサイドマスク
STI 素子分離領域
SW 側壁絶縁膜
SWa 酸化シリコン膜
SWb 窒化シリコン膜
Claims (20)
- (a)半導体基板の表面の上方に、窒化シリコン膜を形成する工程、
(b)前記窒化シリコン膜の上方に、第1配線を形成する工程、
(c)前記第1配線の上に第1絶縁膜を介してアルミニウムを含有する第2配線を形成する工程、
(d)前記第2配線の上に第2絶縁膜を形成する工程、
(e)前記第2配線の上の前記第2絶縁膜を除去することにより、前記第2配線の一部を露出する開口部を形成する工程、
(f)前記(e)工程の後に、露出した前記第2配線の表面に、窒化アルミニウムを形成する工程、
を有し、
前記(a)工程において、前記半導体基板の裏面にも、前記窒化シリコン膜が形成される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程は、前記半導体基板の外周を保持し、前記半導体基板の裏面の少なくとも一部が露出した状態で、化学的気相成長により、前記窒化シリコン膜を成膜する工程である、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記(a)工程は、同一の処理装置内において、複数枚の前記半導体基板のそれぞれについて、前記窒化シリコン膜を形成する工程である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程は、窒素化合物のプラズマ処理である、半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記窒素化合物は、NH3である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
(g)前記(f)工程の後に、前記窒化アルミニウムの上を含む前記第2配線の露出表面に、導電性部材を形成し、前記第2配線と前記導電性部材との電気的接続を図る工程、を有する半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(f)工程の後、前記(g)工程の前に、前記半導体装置を収納容器内で保存する工程、を有する半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記導電性部材は、ボンディングワイヤまたはバンプ電極である、半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
(h)前記(f)工程と、前記(g)工程の間に、前記窒化アルミニウムの上を含む前記第2配線の露出表面に電気信号を印加する試験工程を有する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程は、アルミニウムを含有する導電性膜をエッチングすることにより、前記第2配線を形成する工程であり、
(i)前記(c)工程と、前記(d)工程の間に、第2配線の側壁に酸化アルミニウムを形成する工程、を有する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程は、MISFETのゲート電極の両側に、前記窒化シリコン膜を有する側壁絶縁膜を形成する工程である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程は、MISFETの上部を前記窒化シリコン膜と、前記窒化シリコン膜の上部に位置する酸化シリコン膜との積層膜で覆う工程である、半導体装置の製造方法。 - 半導体基板の表面側の上方に形成された窒化シリコン膜と、
前記窒化シリコン膜の上方に形成された第1配線と、
前記第1配線の上に第1絶縁膜を介して形成されたアルミニウムを含有する第2配線と、
前記第2配線の上に開口部を有する第2絶縁膜と、
前記開口部の底面において、前記第2配線の上に形成された窒化アルミニウムと、
を有する、半導体装置。 - 請求項13記載の半導体装置において、
前記開口部の底面の前記第2配線の上にボンディングワイヤまたはバンプ電極が形成されている、半導体装置。 - 請求項13記載の半導体装置において、
前記開口部の底面の前記第2配線の上にプローブ痕を有する、半導体装置。 - 請求項13記載の半導体装置において、
前記第2配線の側壁に酸化アルミニウムを有する、半導体装置。 - 請求項13記載の半導体装置において、
前記開口部の底面の前記第2配線の上には、前記窒化アルミニウムおよび酸化アルミニウムを有する、半導体装置。 - 請求項13記載の半導体装置において、
前記半導体基板の上に形成されたMISFETを有し、
前記MISFETは、
前記半導体基板の上にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極の側壁に形成された側壁絶縁膜と、
を有し、
前記窒化シリコン膜は、前記側壁絶縁膜を構成する、半導体装置。 - 請求項13記載の半導体装置において、
前記半導体基板の上に形成されたMISFETと、
前記MISFETのソース、ドレイン領域の上に形成された前記窒化シリコン膜と、
前記窒化シリコン膜の上に形成された酸化シリコン膜と、
を有する、半導体装置。 - 請求項13記載の半導体装置において、
前記半導体基板は、ウエハ状態であり、
前記半導体基板の裏面にも、前記窒化シリコン膜が形成されている、半導体装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019135751A (ja) * | 2018-02-05 | 2019-08-15 | エイブリック株式会社 | 半導体装置の製造方法および半導体装置 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016219620A (ja) * | 2015-05-21 | 2016-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法およびそれに用いられるfoup |
US9917027B2 (en) * | 2015-12-30 | 2018-03-13 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with aluminum via structures and methods for fabricating the same |
US9831193B1 (en) | 2016-05-31 | 2017-11-28 | Texas Instruments Incorporated | Methods and apparatus for scribe street probe pads with reduced die chipping during wafer dicing |
KR20180098009A (ko) | 2017-02-24 | 2018-09-03 | 삼성전자주식회사 | 인쇄회로기판 및 이를 가지는 반도체 패키지 |
JP6832755B2 (ja) * | 2017-03-14 | 2021-02-24 | エイブリック株式会社 | 半導体装置および半導体装置の製造方法 |
JP6509300B1 (ja) * | 2017-10-25 | 2019-05-08 | 三菱電機株式会社 | 半導体装置の製造方法 |
US10622324B2 (en) * | 2018-02-08 | 2020-04-14 | Sensors Unlimited, Inc. | Bump structures for high density flip chip interconnection |
US11444025B2 (en) * | 2020-06-18 | 2022-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor and fabrication method thereof |
IT202100014060A1 (it) * | 2021-05-28 | 2022-11-28 | St Microelectronics Srl | Metodo di fabbricazione di uno strato di ridistribuzione, strato di ridistribuzione, circuito integrato e metodo per testare elettricamente il circuito integrato |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04186838A (ja) * | 1990-11-21 | 1992-07-03 | Toshiba Corp | 半導体装置の製造方法 |
JPH04286327A (ja) * | 1991-03-15 | 1992-10-12 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
JP2001032625A (ja) * | 1999-07-19 | 2001-02-06 | Ykk Corp | 自動ドアの安全装置 |
JP2001326225A (ja) * | 2000-05-16 | 2001-11-22 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
JP2005085929A (ja) * | 2003-09-08 | 2005-03-31 | Renesas Technology Corp | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2010003992A (ja) * | 2008-06-23 | 2010-01-07 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
JP2011054818A (ja) * | 2009-09-03 | 2011-03-17 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2012094593A (ja) * | 2010-10-25 | 2012-05-17 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2012174951A (ja) * | 2011-02-23 | 2012-09-10 | Sony Corp | 半導体装置の製造方法、半導体装置、および電子機器 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
US6984591B1 (en) * | 2000-04-20 | 2006-01-10 | International Business Machines Corporation | Precursor source mixtures |
JP2002075996A (ja) | 2000-08-25 | 2002-03-15 | Rohm Co Ltd | 半導体装置およびその製造方法 |
US7332428B2 (en) * | 2005-02-28 | 2008-02-19 | Infineon Technologies Ag | Metal interconnect structure and method |
TW200802703A (en) * | 2005-11-28 | 2008-01-01 | Nxp Bv | Method of forming a self aligned copper capping layer |
JP5014632B2 (ja) * | 2006-01-13 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JP5214913B2 (ja) * | 2007-05-31 | 2013-06-19 | ローム株式会社 | 半導体装置 |
JP2009076653A (ja) * | 2007-09-20 | 2009-04-09 | Toshiba Corp | 半導体装置及びその製造方法 |
KR20090035127A (ko) * | 2007-10-05 | 2009-04-09 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
US7704884B2 (en) * | 2008-04-11 | 2010-04-27 | Micron Technology, Inc. | Semiconductor processing methods |
KR101315880B1 (ko) * | 2008-07-23 | 2013-10-08 | 삼성전자주식회사 | 금속 배선 구조물 및 그 제조 방법 |
JP2010212589A (ja) * | 2009-03-12 | 2010-09-24 | Renesas Electronics Corp | 半導体装置の製造方法 |
US9202713B2 (en) * | 2010-07-26 | 2015-12-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch |
US8872341B2 (en) * | 2010-09-29 | 2014-10-28 | Infineon Technologies Ag | Semiconductor structure having metal oxide or nirtride passivation layer on fill layer and method for making same |
US9576892B2 (en) * | 2013-09-09 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of forming same |
-
2014
- 2014-01-15 JP JP2014005373A patent/JP6300533B2/ja active Active
- 2014-12-31 KR KR1020140194756A patent/KR20150085466A/ko not_active Application Discontinuation
-
2015
- 2015-01-08 US US14/592,730 patent/US9443817B2/en active Active
- 2015-01-14 TW TW104101225A patent/TW201528371A/zh unknown
- 2015-01-14 CN CN201510018698.4A patent/CN104779173A/zh active Pending
-
2016
- 2016-08-16 US US15/238,471 patent/US20160358853A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04186838A (ja) * | 1990-11-21 | 1992-07-03 | Toshiba Corp | 半導体装置の製造方法 |
JPH04286327A (ja) * | 1991-03-15 | 1992-10-12 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
JP2001032625A (ja) * | 1999-07-19 | 2001-02-06 | Ykk Corp | 自動ドアの安全装置 |
JP2001326225A (ja) * | 2000-05-16 | 2001-11-22 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
JP2005085929A (ja) * | 2003-09-08 | 2005-03-31 | Renesas Technology Corp | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JP2010003992A (ja) * | 2008-06-23 | 2010-01-07 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
JP2011054818A (ja) * | 2009-09-03 | 2011-03-17 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2012094593A (ja) * | 2010-10-25 | 2012-05-17 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2012174951A (ja) * | 2011-02-23 | 2012-09-10 | Sony Corp | 半導体装置の製造方法、半導体装置、および電子機器 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019135751A (ja) * | 2018-02-05 | 2019-08-15 | エイブリック株式会社 | 半導体装置の製造方法および半導体装置 |
JP7032159B2 (ja) | 2018-02-05 | 2022-03-08 | エイブリック株式会社 | 半導体装置の製造方法および半導体装置 |
Also Published As
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US20160358853A1 (en) | 2016-12-08 |
KR20150085466A (ko) | 2015-07-23 |
US9443817B2 (en) | 2016-09-13 |
CN104779173A (zh) | 2015-07-15 |
US20150200158A1 (en) | 2015-07-16 |
JP6300533B2 (ja) | 2018-03-28 |
TW201528371A (zh) | 2015-07-16 |
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