CN104779173A - 半导体器件的制造方法及半导体器件 - Google Patents

半导体器件的制造方法及半导体器件 Download PDF

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Publication number
CN104779173A
CN104779173A CN201510018698.4A CN201510018698A CN104779173A CN 104779173 A CN104779173 A CN 104779173A CN 201510018698 A CN201510018698 A CN 201510018698A CN 104779173 A CN104779173 A CN 104779173A
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China
Prior art keywords
film
wiring
semiconductor device
nitride film
aluminium
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CN201510018698.4A
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奥村绫香
堀田胜彦
近藤由宪
大坂宏彰
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN104779173A publication Critical patent/CN104779173A/zh
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Abstract

本发明公开了一种提高半导体器件特性的方法。在含有铝的最上层布线M4上的保护膜PRO上，形成开口部OA1使布线M4的焊接区域PD1露出，并在露出的布线M4的表面上形成氮化铝。接着，在具有所述布线M4的半导体衬底的背面形成氮化硅膜。如上所述，通过在焊接区域PD1上设置氮化铝膜M4e，便可防止因半导体衬底背面的氮化硅膜引起的在焊接区域PD1上产生异物的现象。尤其在焊接区域PD1的形成工序之后，即使至检查工序及焊接工序为止还需要时间，也可防止在焊接区域PD1中异物的生成反应，从而提高半导体器件的特性。

Description

半导体器件的制造方法及半导体器件
技术领域
本发明涉及一种半导体器件的制造方法及半导体器件，例如涉及一种可适用于具有焊接区域的半导体器件的制造方法及具有焊接区域的半导体器件的技术。
背景技术
具有MISFET等半导体元件及布线的半导体器件是通过在半导体衬底上层积氧化硅膜、氮化硅膜等绝缘膜、半导体膜及导电性膜而形成的。如上所述，所述半导体元件经由多层布线与焊接区域电连接。所述焊接区域经由键合线及凸块电极等与外部端子耦合。
例如，在日本特开2002－75996号公报(专利文献1)中公开了如下技术，即在对钝化膜进行蚀刻的工序之后，再用含有氟化铵的液体对布线层表面进行蚀刻，便可防止焊垫的接触不良。
另外，在日本特开1992－186838号公报(专利文献2)中，公开了如下技术，即：用三氯化硼(BCl3)气体将铝(Al)布线表面的汚染层即Al2O3除去后，在布线表面上形成氮化铝(AlN)的技术。
专利文献1 日本特开2002－75996号公报
专利文献2 日本特开1992－186838号公报
发明内容
本案发明人从事具有焊接区域的半导体器件的研究开发工作，对于如何提高其特性一直锐意探讨。在进行研究的过程中，明确了具有焊接区域的半导体器件还具有进一步改善的余地。
本发明的所述内容及所述内容以外的目的和新特征将在本说明书 的描述及附图说明中写明。
下面对本发明中所公开的具有代表性实施方式中的结构概要进行简单说明。
本发明所公开的具有代表性实施方式的半导体器件制造方法包括如下工序，即：在具有铝的布线上的绝缘膜上形成使布线表面的一部分露出的开口部的工序；以及在所露出的布线的表面上形成氮化铝的工序。
本发明所公开的具有代表性实施方式中的半导体器件形成于含有铝的布线上，且具有包括具有开口部的绝缘膜、以及在开口部底面中在布线上形成的氮化铝。
根据本发明所公开的具有代表性实施方式的半导体器件的制造方法，便可制造出特性良好的半导体器件。
另外，根据本发明所公开的具有代表性实施方式的半导体器件，还可提高半导体器件的特性。
附图说明
图1所示的是第1实施方式中半导体器件结构的截面图。
图2A、图2B所示的分别是第1实施方式及比较例中半导体器件的焊接区域及半导体衬底背面的状态的模式示意截面图。
图3所示的是第1实施方式中半导体器件制造工序的截面图。
图4所示的是第1实施方式中半导体器件制造工序的截面图，即接着图3的半导体器件制造工序的截面图。
图5所示的是第1实施方式中所使用的CVD装置的模式截面图。
图6所示的是第1实施方式中所使用的装置的模式截面图。
图7所示的是第1实施方式中半导体器件制造工序的截面图，即接着图4的半导体器件制造工序的截面图。
图8所示的是第1实施方式中半导体器件制造工序的截面图，即接着图7的半导体器件制造工序的截面图。
图9所示的是第1实施方式中半导体器件制造工序的截面图，即接 着图8的半导体器件制造工序的截面图。
图10所示的是第1实施方式中半导体器件制造工序的截面图，即接着图9的半导体器件制造工序的截面图。
图11所示的是第1实施方式中半导体器件制造工序的截面图，即接着图10的半导体器件制造工序的截面图。
图12所示的是第1实施方式中半导体器件制造工序的截面图，即接着图11的半导体器件制造工序的截面图。
图13所示的是第1实施方式中半导体器件制造工序的截面图，即接着图12的半导体器件制造工序的截面图。
图14所示的是第1实施方式中半导体器件制造工序的截面图，即接着图13的半导体器件制造工序的截面图。
图15所示的是第1实施方式中半导体器件制造工序的截面图，即接着图14的半导体器件制造工序的截面图。
图16所示的是第1实施方式中半导体器件制造工序的截面图，即接着图15的半导体器件制造工序的截面图。
图17所示的是第1实施方式中半导体器件制造工序的截面图，即接着图16的半导体器件制造工序的截面图。
图18所示的是第1实施方式中半导体器件制造工序的截面图，即接着图17的半导体器件制造工序的截面图。
图19所示的是第1实施方式中半导体器件制造工序的截面图，即接着图18的半导体器件制造工序的截面图。
图20所示的是第1实施方式中半导体器件制造工序的截面图，即接着图19的半导体器件制造工序的截面图。
图21所示的是第1实施方式中半导体器件制造工序的截面图，即接着图20的半导体器件制造工序的截面图。
图22所示的是第1实施方式中半导体器件制造工序的截面图，即接着图21的半导体器件制造工序的截面图。
图23所示的是第1实施方式中半导体器件制造工序的截面图，即接着图22的半导体器件制造工序的截面图。
图24所示的是第1实施方式中半导体器件制造工序的截面图，即接着图23的半导体器件制造工序的截面图。
图25所示的是第1实施方式中半导体器件制造工序的截面图，即接着图24的半导体器件制造工序的截面图。
图26所示的是第1实施方式中半导体器件制造工序的截面图，即接着图25的半导体器件制造工序的截面图。
图27所示的是第1实施方式中应用例的半导体器件焊接区域结构的截面图。
图28所示的是焊接区域的积层膜的其他结构的截面图。
图29所示的是NH3的等离子处理的有无与产生腐蚀的数量的关系的图表。
图30所示的是第2实施方式中半导体器件结构的截面图。
符号说明
100    装置
100a   流体缸
100b   气体导入孔
100c   板台
BP     突起电极
GE     栅极电极
GI     栅极绝缘膜
IL     层间绝缘膜
IL1    层间绝缘膜
IL1a   氮化硅膜
IL1b   氧化硅膜
IL2    层间绝缘膜
IL3    层间绝缘膜
IL4    层间绝缘膜
IL5    层间绝缘膜
IL5a     氮化硅膜
IL5b     氧化硅膜
M        金属膜
M1       布线
M2       布线
M3       布线
M4       布线
M4a      钛/氮化钛膜
M4b      铝膜
M4c      钛膜
M4d      氧化铝膜
M4e      氮化铝膜
M4f      氧化铝
MN       掩模
MP       掩模
NM       n－型半导体区域
NP       n+型半导体区域
NT       n沟道型MISFET
NW       n型阱
OA1      开口部
OA2      开口部
P1       插塞
P2       插塞
P3       插塞
P4       插塞
PA       异物
PD1      焊接区域
PD2      焊接区域
PI       保护膜
PIN     区域(针孔)
PM      p－型半导体区域
PP      p+型半导体区域
PRO     保护膜
PROa    氮化硅膜
PROb    氧化硅膜
PT      p沟道型MISFET
PW      p型阱
RW      二次布线
RWa     铝膜
RWb     氮化铝膜
S       半导体衬底
SIL     金属硅化物膜
SM      硅化物掩模
STI     元件隔离区
SW      侧壁绝缘膜
SWa     氧化硅膜
SWb     氮化硅膜
具体实施方式
在以下实施方式中，为了方便，在必要时将几个部分或将实施方式分割来说明，除了需要特别说明的以外，这些都不是彼此独立且无关系的，而是与其它一部分或者全部的变形例、应用例、详细内容及补充说明等相互关联的。另外，在以下实施方式中提及要素数等(包括个数、数值、量、范围等)时，除了特别说明及原理上已经明确限定了特定的数量等除外，所述特定数并非指固定的数量，而是可大于等于该特定数或可小于等于该特定数。
而且，在以下实施方式中，除了特别说明及原理上已经明确了是必要时除外，所述构成要素(包括要素步骤等)也并非是必须的要素。同 样地，在以下实施方式中提及的构成要素等的形状、位置关系等时，除了特别说明时及原理上已经明确了并非如此时，实质上包括与前述形状等相近或者类似的。同理，所述数值及范围也同样包括与其相近的。
以下根据附图详细说明本发明的实施方式。为了说明实施方式的所有图中，原则上对具有同一功能的构件采用相同或相关联的符号，并省略掉重复的说明。另外，如果具有多个类似的构件(部位)时，有时会在总称的符号上追加记号或是示出个别或特定位置。另外，以下实施方式中，除了需要特别说明的以外，对具有同一或同样的部分原则上不进行重复说明。
另外，在实施方式所用的图中，为了使图面简单易懂，有时会省略掉截面图中的截面线。
截面图中各部位的大小并非与实际器件对应，为了使图面简单易懂，有时会将特定部位扩大显示。
(第1实施方式)
下面参照附图对本实施方式的半导体器件的结构进行说明。
[结构说明]
图1所示的是本实施方式中半导体器件结构的截面图。本实施方式中的半导体器件具有n沟道型MISFET(NT)及p沟道型MISFET(PT)。
n沟道型MISFET(NT)具有：经由栅极绝缘膜GI配置在衬底S(p型阱PW)上的栅极电极GE，配置在所述栅极电极GE两侧的半导体衬底S(p型阱PW)中的源极、以及漏极区域。其中，在栅极电极GE的侧壁部上形成有由绝缘膜构成的侧壁绝缘膜SW。所述绝缘膜为氧化硅膜SWa和氮化硅膜SWb的积层膜。另外，源极、漏极区域具有LDD结构，并由n+型半导体区域NP和n－型半导体区域NM构成。n－型半导体区域NM对于栅极电极GE的侧壁自对准形成，n+型半导体区域NP对于侧壁绝缘膜SW的侧面自对准形成，而且n+型半导体区域NP结深比n－型半导体区域NM深且杂质浓度也很高。n沟道型MISFET(NT)的栅极长度如为不超过150nm的细微的长度。
p沟道型MISFET(PT)包括：经由栅极绝缘膜GI配置在半导体衬底S(n型阱NW)上的栅极电极GE；配置在所述栅极电极GE两侧的半导体衬底S(n型阱NW)中的源极、以及漏极区域。栅极电极GE的侧壁部上形成有由绝缘膜构成的侧壁绝缘膜SW。可用氧化硅膜SWa和氮化硅膜SWb的积层膜作为绝缘膜。另外，源极、漏极区域具有LDD结构，且由p+型半导体区域PP和p－型半导体区域PM构成。p－型半导体区域PM对于栅极电极GE的侧壁自对准形成；p+型半导体区域PP对于侧壁绝缘膜SW的侧面自对准形成，而且p+型半导体区域PP的结深比p－型半导体区域PM深且杂质浓度也很高。p沟道型MISFET(PT)的栅极长度如为不超过150nm的细微的长度。
另外，MISFET(NT、PT)上形成有层间绝缘膜IL1，且在所述层间绝缘膜IL1上形成有布线M1。MISFET(NT、PT)的源极、漏极区域经由插塞P1与布线M1耦合。所述插塞P1形成于层间绝缘膜IL1中。所述层间绝缘膜IL1如由位于下层的氮化硅膜IL1a、以及位于所述氮化硅膜IL1a上的氧化硅膜IL1b的积层膜构成。
另外，布线M1上形成有层间绝缘膜IL2，所述层间绝缘膜IL2上形成有布线M2。所述布线M1和布线M2经由形成于层间绝缘膜IL2中的插塞P2而被耦合。布线M2上形成有层间绝缘膜IL3，且在所述层间绝缘膜IL3形成有布线M3。所述布线M2和布线M3经由形成于层间绝缘膜IL3中的插塞P3而耦合。另外，布线M3上形成有层间绝缘膜IL4，且在所述层间绝缘膜IL4上形成有布线M4。所述布线M3和布线M4经由形成于层间绝缘膜IL4中的插塞P4而被耦合。 
布线M4上形成有保护膜PRO。所述保护膜PRO中设有开口部OA1，且从开口部OA1的底部露出布线M4的一部分。所述布线M4的露出部被称为焊接区域PD1。布线M4为含有铝的布线。换言之即是，布线M4包括铝膜。此时所说的铝膜并不仅限于纯铝膜，而是以铝为主成分的导电材料膜(但需为能体现金属传导的导电材料膜)。因此，如为具有Al(铝)和Si(硅)的化合物膜或合金膜等。另外，所述铝膜中的Al(铝)的构成比优选比50atom％(原子百分比)大(即富铝)。
本实施方式的半导体器件中，布线M4为最上层布线，通过布线(M1～M4)可使半导体元件(如上述的MISFET)实现所需的布线连接，以及实现所期望的动作。因此，利用布线(最上层布线)M4的露出部即焊接区域PD1，便可对半导体器件是否能实现所期望的动作进行测试(测试工序)。
另外，如后所述，在焊接区域PD1上还形成有由导电性部件构成的突起电极(凸块电极)BP。另外，也可在焊接区域PD1上与由导电性部件构成的键合线耦合(请参照图26)。
本实施方式中，在含有铝的布线(最上层布线)M4的焊接区域PD1(露出表面)上形成氮化铝膜M4e，便可防止布线M4受到腐蚀。下面详细说明其理由。
图2A、图2B所示的分别是本实施方式及比较例中半导体器件的焊接区域及半导体衬底的背面的状态的模式示意截面图。图2A所示的是本实施方式中半导体器件的状态示意图，图2B所示的是比较例中半导体器件的状态示意图。
如图2B所示，插塞P4上的布线M4具有钛/氮化钛膜M4a、铝膜M4b及钛膜M4c。钛/氮化钛膜M4a为钛膜及在其上形成的氮化钛膜的积层膜。布线M4上之上形成有保护膜PRO，并从所述保护膜PRO中的开口部OA1(焊接区域PD1)的底部露出铝膜M4b的主面。换言之就是，除去布线M4上的焊接区域PD1上的保护膜PRO及钛膜M4c，从而使铝膜M4b露出。比较例中，在所述铝膜M4b的露出部上生成异物PA。
此时，在半导体衬底S的背面上形成有氮化硅膜(SiN)及氧化硅膜(SiO2)。图2B中，省略了在层间绝缘膜IL中形成的位于插塞P4更下层的布线、插塞及MISFET(NT、PT)。
如图2A所示，本实施方式中，插塞P4上的布线M4具有钛/氮化钛膜M4a、铝膜M4b及钛膜M4c。布线M4上形成有保护膜PRO，并从所述保护膜PRO中的开口部OA1(焊接区域PD1)的底部露出铝膜M4b的主面。换言之就是，除去布线M4上的焊接区域PD1上的保护膜PRO及钛膜M4c，从而露出铝膜M4b。此时，所述铝膜M4b上形成有氮化铝膜 M4e。而且，半导体衬底S的背面上也形成有氮化硅膜(SiN)及氧化硅膜(SiO2)。如后所述，在半导体器件的制造工序中，通过使用批次式成膜装置形成这些绝缘膜。另外，图2A中，省略了在层间绝缘膜IL中形成的位于插塞P4更下层的布线、插塞及MISFET(NT、PT)。
根据本案发明人所做的研究，与比较例中的半导体器件一样，如果从焊接区域PD1露出铝膜M4b时，从焊接区域PD1露出的铝膜M4b将被腐蚀。更具体地说就是，在从焊接区域PD1露出的铝膜M4b的表面上将产生不期望出现的反应物(异物PA)(请参照图2B)。
经过研究后本案发明人明确了如下情况，即与半导体衬底S的背面上没形成有膜的半导体器件相比，在背面形成有膜的半导体器件中更容易产生上述反应物。而且，与半导体衬底S的背面上没形成有膜的半导体器件相比，背面形成有膜的半导体器件中NH4 +的产生量很多。
由此，可认定在铝膜M4b的表面形成的不希望出现的反应物(异物PA)中，与在半导体衬底的背面上形成的氮化硅膜有关。
即，明确了在半导体衬底S的背面形成有氮化硅膜(SiN)时，因所述氮化硅膜(SiN)而导致NH4 +的产生量增加。因所述NH4 +与Al(Al离子)的反应，Al(OH)3被作为异物而沉淀下来。
下面说明Al(OH)3产生的反应。
2Al＝2Al3 ++6e－…  (化学式1)
6NH3+6H2O＝6NH4 ++6OH－…  (化学式2)
2Al3 ++6HO－＝2Al(OH)3↓…  (化学式3)
6NH4 ++6e－＝6NH3+3H2↑…  (化学式4)
如上所述，在产生异物(Al(OH)3)时，便不可在焊接区域PD1上形成精度良好的导电性部件(凸块电极、键合线)，从而导致不良产生。
而且，根据本案发明人的研究，即使在半导体衬底的背面形成的氮化硅膜被氧化硅膜等覆盖时，将产生穿过氧化硅膜中的NH4 +。
因此，在半导体器件的制造工序中，如果在半导体衬底的背面即使仅形成一次氮化硅膜，也将因所述氮化硅膜而导致产生异物(Al(OH)3)。
另外，在焊接区域PD1的形成工序之后，还具有检查工序及焊接工序等后道工序。在半导体器件的制造工序中，至进行检查工序及焊接工序为止有时还需要时间。例如，有时需要在传送盒(也称FOUP、基板收纳容器、基板包装容器)内保管1个星期及以上。如上所述，如果需要较长的保管时期时，将导致上述Al(OH)3生成反应的进行。另外，有时需在与之前的生产线不同的位置上进行检查工序及焊接工序，包括传送盒的运送工序等，有可能导致保管期间变得更长。此时，也将导致上述Al(OH)3生成反应的进行。
对此，根据本实施方式，由于在焊接区域PD1上设置有氮化铝膜M4e，所以可防止在焊接区域PD1中异物的生成反应。尤其是在焊接区域PD1的形成工序之后，即使至进行检查工序及焊接工序为止需要时间，也可防止在焊接区域PD1中异物的生成反应。
而且，由于焊接区域PD1上的氮化铝膜M4e为薄膜(10nm及以下)，所以在将导电性部件(凸块电极、键合线)向焊接区域PD1上进行按压的工序中将容易将其压碎，从而可提高导电性材料和焊接区域PD1(布线M4)之间的电导通性。
[制法说明]
下面参照图3至图26对本实施方式中的半导体器件的制造方法进行说明。图3至图26(除了图5、图6)所示的是本实施方式中半导体器件制造工序的截面图。
如图3所示，可准备具有～10Ωcm左右的比电阻的p型单结晶硅构成的硅衬底作为半导体衬底(晶片)S。当然，也可用硅衬底以外的半导体衬底S。
接下来在半导体衬底S的主面上形成元件隔离区STI。例如，在半导体衬底S中形成元件隔离沟，再通过将氧化硅膜等绝缘膜填埋进所述元件隔离沟的内部，便可形成元件隔离区STI。另外，也可通过LOCOS(local Oxidation of silicon，硅的局部氧化)法来形成元件隔离区。
接下来，在半导体衬底S的n沟道型MISFET(NT)的形成区域形成p型阱PW，并在p沟道型MISFET(PT)的形成区域形成n型阱NW。
例如，如图4所示，通过掩模MN来覆盖p沟道型MISFET(PT)的形成区域，通过离子注入来注入p型杂质(硼离子(B)等)而形成p型阱PW(图7)。掩模MN如由氧化硅膜构成，并可通过CVD(Chemical Vapor Deposition：化学气相沉积)法等形成。在半导体衬底S的整个面上，在形成将被作为掩模MN的氧化硅膜后，使用光刻技术及蚀刻技术对其进行图案化，便可除去p沟道型MISFET(PT)的形成区域以外的掩模MN。
此时，对于多个半导体衬底S，也可同时形成掩模MN(氧化硅膜)。图5所示的是本实施方式中所使用的CVD装置的模式截面图。图5所示的CVD装置100中，在流体缸(处理室、炉)100a的内部收纳有多个半导体衬底(晶片)S，从气体导入孔100b导入的原料气体被晒之后在半导体衬底S的整个面上形成掩模MN(氧化硅膜)。此时，半导体衬底S的背面的外周部由支撑部支撑(支持)，而背部的大部分都从支撑部露出，所以掩模MN(氧化硅膜)不仅形成在半导体衬底S的表面侧(图5中的上侧)，也形成在背面侧(图5中的下侧)(请参照图4)。上述可将多个半导体衬底S同时进行处理的装置有时也被称为批次式装置。
相反地，图6所示的装置为将半导体衬底S进行逐个处理的装置。图6所示的是本实施方式中所使用的装置的模式截面图。这类装置有时也被称为单片式装置。例如，如通过上述单片式CVD装置成膜时，在流体缸(处理室)100a内的板台(基板搭载台)100c上搭载有半导体衬底(晶片)S，并通过从气体导入孔(图中未示出)导入的原料气体在半导体衬底S的整个面上形成膜。通过上述单片式CVD装置进行处理时，由于半导体衬底S的背面与板台100c接触，所以在半导体衬底S的背面侧不会形成膜。另外，图6所示的“单片式”的装置不仅可用于CVD装置等成膜装置，还可用于干蚀刻装置等的处理装置。
因此，如上所述，通过批次式装置形成掩模MN(氧化硅膜)时，在半导体衬底S的背面侧也形成掩模MN(请参照图4)。而且，在通过单片式蚀刻装置进行蚀刻时，半导体衬底S的背面侧的掩模MN并不被除去而是仍为残留下来的状态(请参照图4)。另外，在后文所述的处 理工序中，除了明确说明的情况之外，都是通过单片式装置进行处理的。
将掩模MN作为掩模形成p型阱PW后，如图8所示，将由氧化硅膜构成的掩模MP将n沟道型MISFET(NT)的形成区域进行覆盖，再注入n型杂质(砷(As)或磷(P)等)离子，以形成n型阱NW。此时所形成的掩模MP也与掩模MN一样，在半导体衬底S的背面侧也形成。因此，在半导体衬底S的背面上，从基板侧开始形成掩模MN及掩模MP的积层膜。接下来进行热处理，将已注入的杂质进行活性化，再通过干蚀刻将掩模MP(氧化硅膜)除去。
接下来如图9所示，在半导体衬底S的主面(p型阱PW、n型阱NW的主面)上，经由栅极绝缘膜GI形成栅极电极GE。例如，通过将半导体衬底S的主面(p型阱PW、n型阱NW的主面)进行热氧化，便可形成由氧化硅膜构成的栅极绝缘膜GI。除了氧化硅膜，也可用氮化硅膜或氮氧化硅膜作为栅极绝缘膜GI。另外，也可用高介电常数膜(即所谓的high-k膜)作为栅极绝缘膜GI。除了热氧化法以外，也可用CVD法等其他成膜方法来形成栅极绝缘膜GI。
接下来形成作为导电性膜(导电体膜)的硅膜。所述硅膜例如可通过CVD法等将多结晶硅膜来形成。通过光刻技术及蚀刻技术对所述多结晶硅膜进行图案化，便可形成栅极电极GE。另外，根据各MISFET(NT、PT)的特性，也可向构成栅极电极GE的材料(本文中为多结晶硅膜)中注入杂质。
接下来，在各栅极电极GE两侧的半导体衬底S(p型阱PW、n型阱NW)中形成源极及漏极区域。
首先，在栅极电极GE两侧的p型阱PW中注入砷(As)或磷(P)等n型杂质，以形成n－型半导体区域NM(图9)。n－型半导体区域NM对于栅极电极GE的侧壁自对准形成。另外，向栅极电极GE两侧的n型阱NW中注入硼离子(B)等p型杂质，以形成p－型半导体区域PM(图9)。p－型半导体区域PM对于栅极电极GE的侧壁自对准形成。
接下来，在栅极电极GE的侧壁部上形成侧壁绝缘膜(Side-Wall膜) SW。如图10所示，在半导体衬底S的整个主面上形成构成侧壁绝缘膜SW的绝缘膜。本实施方式中使用氧化硅膜SWa和氮化硅膜SWb的积层膜。在半导体衬底S的整个主面上，如使用批次式CVD装置形成氧化硅膜SWa。接下来，如使用批次式低压CVD装置在氧化硅膜SWa上形成氮化硅膜SWb。由此，便可在半导体衬底S的整个主面上形成氧化硅膜SWa和氮化硅膜SWb的积层膜。此时，与上述形成掩模MP、MN时一样，在半导体衬底S的背面也将形成氧化硅膜SWa和氮化硅膜SWb的积层膜。因此，在半导体衬底S的背面，从基板侧起形成有掩模MN、掩模MP、氧化硅膜SWa及氮化硅膜SWb的积层膜。另外，除了氧化硅膜SWa和氮化硅膜SWb的积层膜之外，也可用单层的氧化硅膜或单层的氮化硅膜等绝缘膜形成侧壁绝缘膜SW。
接下来如图11所示，通过对氧化硅膜SWa和氮化硅膜SWb的积层膜进行回蚀，以在栅极电极GE的侧壁部上形成侧壁绝缘膜SW。所述积层膜的回蚀是通过单片式蚀刻装置进行的。因此，半导体衬底S的背面侧的氧化硅膜SWa和氮化硅膜SWb的积层膜并没被除去而是仍处于残留的状态。
接下来如图12所示，通过向栅极电极GE和侧壁绝缘膜SW的合成体两侧的p型阱PW中注入砷(As)或磷(P)等n型杂质，以形成n+型半导体区域NP。n+型半导体区域NP对于侧壁绝缘膜SW的侧壁自对准形成。n+型半导体区域NP是一个杂质浓度比n－型半导体区域NM高、且结深很深的半导体区域。另外，通过向栅极电极GE和侧壁绝缘膜SW的合成体两侧的n型阱NW中注入硼(B)等p型杂质，以形成p+型半导体区域PP。p +型半导体区域PP对于侧壁绝缘膜SW的侧壁自对准形成。p+型半导体区域PP是一个杂质浓度比p－型半导体区域PM高、且结深很深的半导体区域。接下来进行热处理以使所注入的杂质活性化。由此，便可在栅极电极GE两侧的p型阱PW中形成由n－型半导体区域NM和n+型半导体区域NP构成的LDD结构的源极及漏极区域，并在栅极电极GE两侧的n型阱NW中形成由p－型半导体区域PM和p+型半导体区域PP构成的LDD结构的源极及漏极区域。
通过进行上述工序后，便可在p型阱PW的主表面上形成n沟道型MISFET(NT)，且在n型阱NW的主表面上形成p沟道型MISFET(PT)。
接下来，使用自对准金属硅化物(Self-Aligned siliCIDE)技术，分别在栅极电极GE、n+型半导体区域NP及p+型半导体区域PP的上部形成金属硅化物膜SIL。
首先，如通过批次式CVD装置，在没形成有金属硅化物膜SIL的区域(图中未示出)中，使氧化硅膜形成为硅化物掩模SM的氧化硅膜(请参照图13)。此时，与形成上述掩模MP、掩模MN、及氧化硅膜SWa和氮化硅膜SWb的积层膜时一样，在半导体衬底S的背面也形成有硅化物掩模SM(氧化硅膜)。因此，在半导体衬底S的背面上，从基板侧起将形成掩模MN、掩模MP、氧化硅膜SWa及氮化硅膜SWb的积层膜、以及硅化物掩模SM。
接下来，使用光刻技术及蚀刻技术，将n沟道型MISFET(NT)及p沟道型MISFET(PT)上的硅化物掩模SM(氧化硅膜)除去(请参照图13)。
接下来如图13所示、在半导体衬底S的整个面上形成金属膜M，并通过热处理使栅极电极GE、n+型半导体区域NP及p+型半导体区域PP与金属膜M发生反应。由此，便可在栅极电极GE、n+型半导体区域NP及p+型半导体区域PP的上部分别形成金属硅化物膜SIL。上述金属膜如可通过溅射法等由钴(Co)膜或镍(Ni)膜等构成。接下来除去未发生反应的金属膜M(请参照图14)。另外，也可省略掉金属硅化物膜SIL的形成工序。 
接下来，在n沟道型MISFET(NT)及p沟道型MISFET(PT)上形成绝缘膜(层间绝缘膜)IL1。首先如图15所示，以覆盖MISFET(NT、PT)的源极、漏极区域及栅极电极GE的上方的方式形成氮化硅膜IL1a。所述氮化硅膜IL1a通过使用批次式CVD装置来形成。此时，与形成上述掩模MP、掩模MN等一样，在半导体衬底S的背面上也形成氮化硅膜IL1a。因此，半导体衬底S的背面上，从基板侧起形成有掩模MN、掩模MP、氧化硅膜SWa及氮化硅膜SWb的积层膜、硅化物掩模SM及氮化硅膜IL1a等。
接下来如图16所示，通过CVD法等在氮化硅膜IL1a上形成比所述氮化硅膜IL1a厚的氧化硅膜IL1b。由此，便可形成由氮化硅膜IL1a及氧化硅膜IL1b的积层膜构成的层间绝缘膜IL1。在形成所述层间绝缘膜IL1之后，根据需要，通过CMP法等对层间绝缘膜IL1的上表面进行平坦化。
接下来如图17所示，通过光刻技术及蚀刻技术选择性地除去层间绝缘膜IL1，便可在层间绝缘膜IL1中形成接触孔。此时，利用氮化硅膜IL1a和氧化硅膜IL1b的蚀刻选择比，首先对氧化硅膜IL1b进行蚀刻，并进一步对所露出的氮化硅膜IL1a进行蚀刻，便可形成精度良好的接触孔。
接下来，在包括接触孔内的层间绝缘膜IL1上形成阻挡导体膜(图中未示出)及主导体膜的积层膜。接着通过CMP法或回蚀法等除去层间绝缘膜IL1上多余的主导体膜及阻挡导体膜，以形成插塞P1。所述插塞P1如为经由金属硅化物膜SIL而在n+型半导体区域NP及p+型半导体区域PP的上部形成。另外，也可在栅极电极GE的上部形成插塞P1，而且，也可用如钛膜、氮化钛膜、或这些膜的积层膜来作为阻挡导体膜。也可使用钨膜等作为主导体膜。
接下来，在被插塞P1填埋的层间绝缘膜IL1上形成由导电性膜构成的布线M1。例如，在层间绝缘膜IL1及插塞P1上，通过溅射法等，依次堆积钛/氮化钛膜、铝膜、以及由钛/氮化钛膜构成的积层膜，以作为导电性膜。钛/氮化钛膜的积层膜也被称为阻挡导体膜。接下来，通过光刻技术及蚀刻技术对上述积层膜进行图案化，以在插塞P1上形成布线M1。
用于形成布线M1的上述铝膜并不仅限于纯铝膜，也可使用以铝为主成分的导电材料膜(但需为能体现金属传导的导电材料膜)，例如，也可使用Al(铝)和Si(硅)的化合物膜或者合金膜。另外，所述铝膜中Al(铝)的构成优选比50％的原子百分比大(即富铝)，这不仅是用于形成布线M1的上述铝膜，用于形成布线M2～M3的铝膜也同样。
接下来如图18所示，在布线M1上形成层间绝缘膜IL2。例如，通过CVD法等在布线M1上堆积氧化硅膜。
接下来通过光刻技术及蚀刻技术选择性地除去层间绝缘膜IL2，以在层间绝缘膜IL2中形成接触孔。接着通过在接触孔内部填埋导电性膜，以在层间绝缘膜IL2中形成插塞P2。所述插塞P2也可通过与形成插塞P1同样的方法形成。接着在插塞P2上形成由导电性膜构成的布线M2。例如，使用溅射法等依次在间绝缘膜IL2及插塞P2上堆积钛/氮化钛膜、铝膜、以及由钛/氮化钛膜构成的积层膜，以作为导电性膜。接下来用光刻技术及蚀刻技术对上述积层膜进行图案化，以在上述插塞P2上形成布线M2。
接下来如图19所示，在布线M2上形成层间绝缘膜IL3。例如，通过CVD法等在布线M2上堆积氧化硅膜。接下来通过光刻技术及蚀刻技术选择性地除去层间绝缘膜IL3，以在层间绝缘膜IL3中形成接触孔。接着通过在接触孔内部填埋导电性膜，便可在层间绝缘膜IL3中形成插塞P3。所述插塞P3可通过与形成插塞P1同样的方法来形成。接下来在插塞P3上形成由导电性膜构成的布线M3。例如，通过溅射法等在层间绝缘膜IL3及插塞P3上依次堆积钛/氮化钛膜、铝膜、以及由钛/氮化钛膜构成的积层膜，以作为导电性膜。接下来使用光刻技术及蚀刻技术对所述积层膜进行图案化，以在所述插塞P3上形成布线M3。
接下来如图20所示，在布线M2上形成层间绝缘膜IL4。例如，通过CVD法等在布线M3上堆积氧化硅膜。接下来通过光刻技术及蚀刻技术选择性地除去层间绝缘膜IL4，以在层间绝缘膜IL4中形成接触孔。接着通过在接触孔内部填埋导电性膜，以在层间绝缘膜IL4中形成插塞P4。所述插塞P4可通过与形成插塞P1同样的方法来形成。
接下来如图21所示，在插塞P4上形成由导电性膜构成的布线M4。例如，通过溅射法等在层间绝缘膜IL4及插塞P4上依次堆积钛/氮化钛膜M4a、铝膜M4b以及由钛膜M4c构成的积层膜等，作为导电性膜。接下来，通过光刻技术及蚀刻技术对上述积层膜进行图案化，以在上述插塞P4上形成布线M4。另外，对布线M4进行图案化时，例如也可形成氮氧化硅膜作为反射防止膜。可在对布线M4进行图案化后除去所述氮氧化硅膜，也可使其残留在布线M4上。
接下来如图22所示，对布线M4的侧面(铝膜M4b的侧面)进行钝化处理(氧化处理)。例如，通过对布线M4进行氧的等离子处理，以在布线M4的侧面(铝膜M4b的侧面)上形成氧化铝膜(Al2O3膜)M4d。例如，在以下条件下，即：板台温度：250℃；高频功率：2000W；处理室内压力：100Pa；O2气体流量：7000mL/min(sccm)的条件下，进行120秒的处理。根据相关处理，便可在布线M4的侧面上形成膜厚为1～5nm左右的氧化铝膜。另外，钝化处理(氧化处理)除了可使用氧气以外，也可用臭氧(O3)进行处理。
接下来如图23所示，在布线M4上形成保护膜PRO。例如，通过CVD法等在包括布线M4之上的层间绝缘膜IL4上堆积氮化硅膜PROa，而且，还通过CVD法等在所述氮化硅膜PROa上堆积氧化硅膜PROb。
接下来如图24所示，通过除去布线M4(铝膜M4b)的焊接区域PD1上的保护膜PRO，以形成开口部OA1。例如，在保护膜PRO上形成在开口部OA1的形成区域中具有开口部的光致抗蚀膜，并将所述光致抗蚀膜作为掩模对保护膜PRO进行蚀刻。在残留有反射防止膜时，也对该反射防止膜进行蚀刻。接下来，进一步对露出的钛膜M4c进行蚀刻。由此，便可使焊接区域PD1的铝膜M4b露出。换言之就是，铝膜M4b的焊接区域PD1从开口部OA1的底面露出。
接下来如图25所示，通过对铝膜M4b的焊接区域PD1进行氮化，以形成氮化铝膜(AlN膜)M4e。例如，进行氨(NH3)的等离子处理。在如下条件下，即：板台温度：400℃；高频功率：270W；处理室内压力：660Pa；NH3气体流量：145mL/min(sccm)的条件下进行20秒的处理。另外，氮化处理是通过使用氮(N2)或氨(NH3)等的氮化合物气体进行的等离子处理。
根据相关处理，便可在焊接区域PD1的表面上形成膜厚为3～6nm左右的氮化铝膜(AlN膜)。所述氮化铝膜(AlN膜)优选膜厚不满10nm的氮化铝膜。
接下来利用焊接区域PD1，对半导体器件是否实现了所期望的动作进行测试(实验)。例如，通过将探针插进焊接区域PD1，并施加规定 的电信号后，确认其是否实现了所期望的动作。此时，氮化铝膜(AlN膜)的膜厚仅为几nm，所以探针可很容易地刺破该膜，不会出现探针和焊接区域PD1之间出现电导通的障碍。因进行该测试工序，所以将在焊接区域PD1中留下针痕。
之后，对半导体衬底S的背面进行研磨，使半导体衬底S实现薄膜化后，切断(切割)半导体衬底S以将之分(划片)为多个半导体芯片。由此，便可从半导体衬底S(半导体晶片)的各芯片区域获得半导体芯片。
接下来如图26所示，在焊接区域PD1上形成由导电性部件构成的突起电极(凸块电极)BP(焊接工序)。导电性部件如由金或含有金的合金构成。例如，通过电焊枪使由金构成的引线的尖端形成金球，并在将金球按压到焊接区域PD1上之后，再切断与金球耦合的引线。之后将金球凸点搭载到布线基板等之上形成的外部端子(布线、引线)上，将其进行电连接，便可将半导体器件(芯片)进行安装。另外，也可通过键合线将焊接区域PD1和布线(引线)进行电连接。此时，例如通过电焊枪使由金形成的引线的一端形成金球，并将金球按压到焊接区域PD1上之后再将与金球耦合的引线的多个端按压到布线(引线)上。
如上所述，通过将与外部端子电连接的导电性部件(凸块电极、键合线)按压到焊接区域PD1上，氮化铝膜M4e将被割裂(碎裂)，经由氮化铝膜M4e的割裂处，便可提高布线M4和导电性部件(BP)之间电连接的特性。
如上所述，根据本实施方式，由于在焊接区域PD1上设有氮化铝膜M4e，所以即使在半导体衬底的背面形成有氮化硅膜(SWb、IL1a)时，也可防止焊接区域PD1中异物的生成反应。特别是在焊接区域PD1的形成工序之后，至检查工序及焊接工序为止还需要时间，以及在半导体衬底的背面形成氮化硅膜，而且即使焊接区域PD1的露出状态为较长时期时，也可有效防止异物的生成反应。
特别是随着半导体衬底(晶片)的大口径化，对形成于背面的膜的影响很大，例如，使用直径为300mm及以上的半导体衬底(晶片) 时，适用本实施方式尤其具有显著效果。
另外，在上述制造工序中，以氧化硅膜SWa的形成工序及氮化硅膜IL1a的形成工序作为在半导体衬底的背面形成氮化硅膜的工序的示例，但并不仅限于此示例。也可在半导体器件的其他结构部中使用氮化硅膜，其形成工序中，也可在半导体衬底的背面形成氮化硅膜，在此不再赘言。另外，也可使用氮化硅膜作为各种处理工序(例如离子注入工序等)中形成的掩模，在该形成工序中，也可在半导体衬底的背面形成氮化硅膜，在此也不再赘言。
(应用例)
在上述制造工序中，形成开口部OA1后，虽然对铝膜M4b的焊接区域PD1进行了氮化处理，但也可在对铝膜M4b的焊接区域PD1进行钝化处理(氧化处理)后再进行氮化处理。另外，由于除了铝膜M4b的焊接区域PD1上的结构之外，其他内容与第1实施方式都相同，所以在此不再进行详细说明。
图27所示的是第1实施方式中应用例的半导体器件焊接区域结构的截面图。如图27所示，在本应用例中，布线M4具有钛/氮化钛膜M4a、铝膜M4b以及钛膜M4c。布线M4的侧壁上形成有氧化铝膜(Al2O3膜)M4d。
另外，在布线M4上形成有保护膜PRO，且在所述保护膜PRO的开口部OA1(焊接区域PD1)中，具有氧化铝膜M4f和氮化铝膜M4e的积层膜。换言之就是，在保护膜PRO的开口部OA1(焊接区域PD1)中，在铝膜M4b上形成有氧化铝膜M4f，而且在所述氧化铝膜M4f上还形成有氮化铝膜M4e。
如上所述，即使在焊接区域PD1上设有氧化铝膜M4f和氮化铝膜M4e的积层膜时，也可防止焊接区域PD1中异物的生成反应。
接下来，对在焊接区域PD1上形成氧化铝膜M4f和氮化铝膜M4e的积层膜的形成工序进行详细说明。
首先，如图24所说明的一样，通过除去布线M4(铝膜M4b)的焊接区域PD1上的保护膜PRO，便可形成开口部OA1，而且，还进一步对 所露出的钛膜M4c进行蚀刻。由此，便可使焊接区域PD1的铝膜M4b露出。
接下来，通过对铝膜M4b的焊接区域PD1进行氧化处理而形成氧化铝膜(Al2O3膜)M4f(请参照图27)。如在以下条件下,即：板台温度：250℃；高频功率:2000W；处理室内压力：100Pa；O2气体流量：7000mL/min(sccm)的条件下进行120秒的氧的等离子处理。
接下来，通过对铝膜M4b的焊接区域PD1进行氮化处理而形成氮化铝膜(AlN膜)。例如在如下条件下，即在：板台温度：400℃；高频功率：270W；处理室内压力；660Pa；NH3气体流量：145mL/min(sccm)的条件下进行20秒的NH3的等离子处理。
在所述NH3的等离子处理中，将氧化铝膜(Al2O3膜)M4f进行还原，并将氧化铝膜转换为铝之后，便可形成氮化铝膜。由此，便可在焊接区域PD1上形成氧化铝膜M4f和氮化铝膜M4e的积层膜。
另外，根据氧化铝膜M4f的膜厚，也有可能所有的积层膜都是氮化铝膜M4e。
另外，由于氧化铝膜M4f难于形成为均一的膜，也有可能形成具有针孔(Pin hole)的不规则的膜。图28所示的是焊接区域的积层膜的其他结构的截面图。如图28所示，也可以填埋没形成有氧化铝膜M4f的区域(针孔)PIN的方式形成氮化铝膜M4e。此时，如可进行N2的等离子处理。由于在N2的等离子处理中没有还原作用，所以在没形成有氧化铝膜M4f的区域(针孔)PIN中将形成有氮化铝膜M4e。
在上述情况下，焊接区域PD1被氧化铝膜M4f或氮化铝膜M4e覆盖的情况下，可防止焊接区域PD1中异物的生成反应。当然，在进行NH3的等离子处理时，也可在包括没形成有氧化铝膜M4f的区域(针孔)PIN的焊接区域PD1的整个面上形成氮化铝膜M4e。
如上所述，也可对焊接区域PD1进行氧化处理和氮化处理。但是，由于所形成的氧化铝膜M4f及氮化铝膜M4e的膜厚分别为5nm及以下和不满10nm的薄膜，所以膜的积层状态也可为各种状态。
图27及图28所示的积层状态的膜只需通过Auger电子能谱(AES)等 检测出氧化铝膜M4f及氮化铝膜M4e的构成元素，便可确认其形成状态。
另外，如前所述，由于氧化铝膜M4f容易成为具有针孔的不规则的膜，所以最好避免由单层的氧化铝膜M4f覆盖焊接区域PD1的状态。如图27或图28所示，由于与氮化铝膜M4e一起形成，所以也可有效防止焊接区域PD1中异物的生成反应。
(实验例)
图29所示的是NH3的等离子处理的有无与产生腐蚀的数量的关系的图表。横轴所示的是晶片号码，纵轴所示的是产生腐蚀的数量--“个”。半导体衬底的背面形成有氮化硅膜，而且，在焊接区域PD1露出的状态下，对放置(保存)了8日的24片晶片(半导体衬底)与放置(保存)了12日的24片晶片(半导体衬底)进行的外观检查实验。
没进行过NH3的等离子处理时(菱形标记)，放置期间越长，腐蚀的产生个数也由2个增加为3个。即，随着放置时间变长，腐蚀产生个数由2个增加到了3个。与此相反，进行了NH3的等离子处理时(正方形标记)与放置期间无关，腐蚀产生个数依然是0个。即，进行了NH3的等离子处理时(正方形标记)与没进行NH3的等离子处理时(菱形标记)相比，腐蚀的产生数量少，即使放置期间很长，腐蚀产生数量依然很少。
如上所述，确定了具有可防止焊接区域PD1上的氮化铝膜M4e产生腐食(异物的生成反应)的效果。
(第2实施方式)
第1实施方式中，虽在焊接区域PD1上形成了由导电性部件构成的突起电极(凸块)BP(请参照图26)，但也可在焊接区域PD1上进行二次布线，并可在二次布线上设置由导电性部件构成的突起电极BP。
图30所示的是本实施方式中半导体器件结构的截面图。由于比布线M4更下层的布线结构与第1实施方式时相同，所以在此不再进行详细说明。
如图30所示，布线M4形成于层间绝缘膜IL4上，且经由插塞P4与 布线M3耦合。
在布线M4上形成有层间绝缘膜IL5。所述层间绝缘膜IL5上设置有开口部OA1，且从开口部OA1的底部露出布线M4的一部分。所述布线M4的露出部被称为焊接区域PD1。布线M4为具有铝的布线。
开口部OA1内及层间绝缘膜IL5上形成有二次布线RW。因此，在开口部OA1的底部(焊接区域PD1)中，布线M4与二次布线RW耦合。二次布线RW为具有铝的布线。
本实施方式的半导体器件中，布线M4为最上层布线，并通过布线(M1～M4)使半导体元件(如上述的MISFET)实现所期望的结线结构，以及获得所期望的动作。因此，利用布线(最上层布线)M4的露出部即焊接区域PD1，便可对半导体器件是否能进行所期望的动作进行测试(测试工序)。
二次布线RW就是将布线(最上层布线)M4的一部分即焊接区域PD1引到芯片所期望的区域(焊接区域PD2)的布线。
二次布线RW上形成有保护膜PI。所述保护膜PI上设有开口部OA2，而从开口部OA2的底部露出二次布线RW的主面。所述二次布线RW的露出部被称为焊接区域PD2。
焊接区域PD2上还形成有由导电性部件构成的突起电极(凸块电极)BP。另外，焊接区域PD2上也可与由导电性部件构成的键合线耦合。
本实施方式中，在含有铝的布线(最上层布线)M4的焊接区域PD1(露出表面)上形成有氮化铝膜M4e，可防止布线M4受到腐蚀。另外，在含有铝的二次布线RW的焊接区域PD2(露出表面)上形成氮化铝膜RWb，便可防止二次布线RW受到腐食。 
如上所述，在焊接区域PD1上形成氮化铝膜M4e时，至检查工序为止还需要时间，且在半导体衬底的背面上形成有氮化硅膜，而且，即使在焊接区域PD1长时间露出时，也可有效防止异物的生成反应。另外，通过在焊接区域PD2上形成氮化铝膜RWb，至焊接工序等的后工序为止还需要时间，半导体衬底的背面还形成有氮化硅膜，而且即使在焊接 区域PD2长时间露出的状态下，也可有效防止异物的生成反应。
接下来对布线M4及二次布线RW的形成工序进行说明。
首先，在布线M4上形成层间绝缘膜IL5。如与第1实施方式一样，通过CVD法等在具有布线M4上的层间绝缘膜IL3上堆积氮化硅膜IL5a，而且，还通过CVD法等在所述氮化硅膜IL5a上堆积氧化硅膜IL5b(请参照图23)。
接下来，通过除去布线M4(铝膜M4b)的焊接区域PD1上的层间绝缘膜IL5，便形成开口部OA1。例如，在层间绝缘膜IL5上形成光致抗蚀膜，并将所述光致抗蚀膜作为掩模对层间绝缘膜IL5进行蚀刻，其中，所述光致抗蚀膜在开口部OA1的形成区域中具有开口部。接着对所露出的钛膜M4c进一步进行蚀刻。由此，便可使焊接区域PD1的铝膜M4b露出(请参照图24)。
接下来，通过使铝膜M4b的焊接区域PD1氮化，以形成氮化铝膜(AlN膜)(请参照图25)。如与第1实施方式一样进行氨(NH3)的等离子处理。
接下来，利用焊接区域PD1对半导体器件是否进行所期望的动作进行测试。例如，将探针插进焊接区域PD1中进行导通试验。此时，由于氮化铝膜(AlN膜)的膜厚仅为几nm，所以探针可很容易地穿透氮化铝膜，所以不会给导通试验带来任何障碍。
接下来，在开口部OA1内及层间绝缘膜IL5上形成由导电性膜构成的二次布线RW。如通过溅射法等在开口部OA1内及层间绝缘膜IL5上堆积铝膜以作为导电性膜。也可用钛/氮化钛膜、铝膜、以及由氮化钛膜构成的积层膜等作为导电性膜。接下来通过光刻技术及蚀刻技术对上述导电性膜进行图案化以形成二次布线RW。
接下来在二次布线RW上形成保护膜PI。例如，使用感光性聚酰亚胺膜在二次布线RW及层间绝缘膜IL5上进行涂布，以作为保护膜PI。
接下来，通过除去二次布线RW(铝膜RWa)的焊接区域PD2上的保护膜PI，以形成开口部OA2。例如，通过对感光性聚酰亚胺膜进行曝光及显影来形成开口部OA2。由此，便可使焊接区域PD2的二次布线(铝 膜)RW露出。另外，在用钛/氮化钛膜、铝膜、以及由氮化钛膜构成的积层膜作为二次布线RW时，焊接区域PD2的氮化钛膜也将被除去，从而使铝膜露出。
接下来，通过对二次布线(铝膜)RW的焊接区域PD2进行氮化，便可形成氮化铝膜(AlN膜)。如与第1实施方式一样进行氨(NH3)的等离子处理。
之后，对半导体衬底S的背面进行研磨，使半导体衬底S薄膜化，将半导体衬底S进行切断(切割)后便可分割(划片)为多个半导体芯片。由此，便可从半导体基板S(半导体晶片)的各芯片区域获得半导体芯片。
接下来，在焊接区域PD2上形成由导电性部件构成的突起电极(凸块电极)BP(焊接工序)。突起电极(凸块电极)BP也可通过与第1实施方式同样的方式形成。另外，也可与第1实施方式一样，在焊接区域PD2上形成键合线。
另外，由于布线M4的焊接区域PD1上的氮化铝膜(AlN膜)因二次布线RW形成时的膜应力而容易被割裂(碎裂)，所以可提高布线M4与二次布线RW之间电导通的特性。另外，在布线M4和二次布线RW之间的耦合抗阻较高时，在二次布线RW的形成工序之前，也可除去布线M4的焊接区域PD1上的氮化铝膜(AlN膜)。
以上根据实施方式具体地说明了本案发明人所作的发明，但是本发明并不受到所述实施方式的限定，在不超出其要旨的范围内能够进行种种变更，在此无需赘言。
例如，在第1实施方式中，布线M1～布线M3是通过图案化而形成的，但也可通过在层间绝缘膜中设置的布线槽中填埋铜(Cu)等导电性膜，即所谓的“嵌入式工艺法”来形成布线M1～布线M3。另外，也可通过在层间绝缘膜中的线槽及其下的接触孔同时填埋铜(Cu)等导电性膜，即所谓的“双镶嵌法”来形成布线及插塞(M2及P2等)。

Claims (20)

1.一种半导体器件的制造方法，其特征在于，包括如下工序：
工序(a)，在半导体衬底的表面的上方形成氮化硅膜；
工序(b)，在所述氮化硅膜的上方形成第1布线；
工序(c)，经由第1绝缘膜在所述第1布线之上形成含有铝的第2布线；
工序(d)，在所述第2布线之上形成第2绝缘膜；
工序(e)，通过除去所述第2布线之上的所述第2绝缘膜，形成使所述第2布线的一部分露出的开口部；以及
工序(f)，在所述工序(e)之后，在露出的所述第2布线的表面上形成氮化铝；
其中，在所述工序(a)中，在所述半导体衬底的背面也形成所述氮化硅膜。
2.如权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(a)是在保持所述半导体衬底的外周且所述半导体衬底的背面的至少一部分露出的状态下，通过化学气相沉积法对所述氮化硅膜进行成膜的工序。
3.如权利要求2所述的半导体器件的制造方法，其特征在于，
所述工序(a)在同一处理装置内，分别在多个所述半导体衬底的每一个上形成所述氮化硅膜。
4.如权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(f)为氮化合物的等离子处理。
5.如权利要求4所述的半导体器件的制造方法，其特征在于，
所述氮化合物为氨(NH3)。
6.如权利要求1所述的半导体器件的制造方法，其特征在于，
还具有工序(g)，所述工序(g)在所述工序(f)之后，在具有所述氮化铝之上的所述第2布线的露出表面上形成导电性部件，并实现所述第2布线与所述导电性部件的电连接。
7.如权利要求6所述的半导体器件的制造方法，其特征在于，
在所述工序(f)之后，且在所述工序(g)之前，还具有将所述半导体器件保存在收纳容器内的工序。
8.如权利要求6所述的半导体器件的制造方法，其特征在于，
所述导电性部件为键合线或凸块电极。
9.如权利要求7所述的半导体器件的制造方法，其特征在于，
还具有实验工序(h)，所述实验工序(h)在所述工序(f)和所述工序(g)之间，对具有所述氮化铝之上的所述第2布线的露出表面施加电信号。
10.如权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(c)为通过对含有铝的导电性膜进行蚀刻，以形成所述第2布线的工序，
所述半导体器件的制造方法还具有工序(i)，所述工序(i)在所述工序(c)和所述工序(d)之间，在第2布线的侧壁形成氧化铝。
11.如权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(a)为在MISFET的栅极电极的两侧形成具有所述氮化硅膜的侧壁绝缘膜的工序。
12.如权利要求1所述的半导体器件的制造方法，其特征在于，
所述工序(a)是通过所述氮化硅膜和位于所述氮化硅膜的上部的氧化硅膜的积层膜覆盖MISFET的上部的工序。
13.一种半导体器件，其特征在于，
具有：
在半导体衬底的表面侧的上方形成的氮化硅膜；
在所述氮化硅膜的上方形成的第1布线；
经由第1绝缘膜在所述第1布线之上形成的含有铝的第2布线；
在所述第2布线之上具有开口部的第2绝缘膜；以及
在所述开口部的底面形成在所述第2布线之上的氮化铝。
14.如权利要求13所述的半导体器件，其特征在于，
在所述开口部的底面的所述第2布线之上形成有键合线或凸块电极。
15.如权利要求13所述的半导体器件，其特征在于，
在所述开口部的底面的所述第2布线之上具有针痕。
16.如权利要求13所述的半导体器件，其特征在于，
在所述第2布线的侧壁上具有氧化铝。
17.如权利要求13所述的半导体器件，其特征在于，
在所述开口部的底面的所述第2布线之上具有所述氮化铝及氧化铝。
18.如权利要求13所述的半导体器件，其特征在于，
还具有形成于所述半导体衬底之上的MISFET；
其中，所述MISFET具有：
经由栅极绝缘膜形成于所述半导体衬底之上的栅极电极；以及
形成于所述栅极电极的侧壁上的侧壁绝缘膜；
其中，所述氮化硅膜构成所述侧壁绝缘膜。
19.如权利要求13所述的半导体器件，其特征在于，具有：
形成于所述半导体衬底之上的MISFET；
形成于所述MISFET的源极区域及漏极区域之上的所述氮化硅膜；以及
形成于所述氮化硅膜之上的氧化硅膜。
20.如权利要求13所述的半导体器件，其特征在于，
所述半导体衬底为晶片状态；
在所述半导体衬底的背面也形成有所述氮化硅膜。
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