JP2015076544A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000015556 catabolic process Effects 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 description 32
- 238000005516 engineering process Methods 0.000 description 11
- 239000010410 layer Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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Abstract
【解決手段】本発明による半導体装置は、終端領域21において、N−型基板1の基板表面9から予め定められた深さ方向に形成された不純物領域であるP−型耐圧保持領域7と、N−基板1上であり、少なくともP−型耐圧保持領域7を覆うように形成された第1の絶縁膜10と、第1の絶縁膜10上に形成された第1のフィールドプレート11と、第1のフィールドプレート11および第1の絶縁膜10を覆うように形成された第2の絶縁膜12と、第2の絶縁膜12上に形成された第2のフィールドプレート13とを備え、第1の絶縁膜10の膜厚は、X方向直線部22およびY方向直線部23よりもコーナー部24の方が厚いことを特徴とする。
【選択図】図3
Description
まず、本発明の前提となる技術(前提技術)について説明する。
図1は、本発明の実施の形態1による半導体装置の構成の一例を示す平面図である。また、図2は、図1のA−A断面の構成の一例を示す断面図であり、終端領域の21のY方向直線部23の断面の構成を示している。また、図3は、図1のB−B断面の構成の一例を示す断面図であり、終端領域21のコーナー部24の断面の構成を示している。なお、図2ではY方向直線部23の断面の構成を示しているが、X方向直線部22の断面の構成も同様である。
図6は、図1のB−B断面の構成の一例を示す断面図であり、終端領域21のコーナー部24の断面の構成を示している。
本発明の実施の形態3では、実施の形態2による凹部領域15がLOCOS(Local Oxidation of Silicon)法によって形成されることを特徴としている。
図10は、図6に示す凹部領域15の周辺部分の拡大図である。
Claims (4)
- 素子領域を平面視で囲むように設けられた、直線部とコーナー部とを有する終端領域を備える半導体装置であって、
前記終端領域において、
第1の導電型の基板の表面から予め定められた深さ方向に形成された第2の導電型の低濃度の不純物領域である耐圧保持領域と、
前記基板上であり、少なくとも前記耐圧保持領域を覆うように形成された第1の絶縁膜と、
前記第1の絶縁膜上に形成された第1のフィールドプレートと、
前記第1のフィールドプレートおよび前記第1の絶縁膜を覆うように形成された第2の絶縁膜と、
前記第2の絶縁膜上に形成された第2のフィールドプレートと、
を備え、
前記第1の絶縁膜の膜厚は、前記直線部よりも前記コーナー部の方が厚いことを特徴とする、半導体装置。 - 前記コーナー部において、前記基板の表面が凹形状に形成された凹部領域をさらに備え、
前記第1の絶縁膜の表面は、前記コーナー部と前記直線部とで面一であることを特徴とする、請求項1に記載の半導体装置。 - 前記凹部領域は、LOCOS(Local Oxidation of Silicon)法によって形成されることを特徴とする、請求項2に記載の半導体装置。
- 前記凹部領域は、非凹部領域との境界面が前記基板の表面に対して90度以下の傾斜を有するテーパー形状で形成されることを特徴とする、請求項2または3に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013212639A JP6168961B2 (ja) | 2013-10-10 | 2013-10-10 | 半導体装置 |
US14/220,007 US9871109B2 (en) | 2013-10-10 | 2014-03-19 | Semiconductor device |
DE102014208306.0A DE102014208306B4 (de) | 2013-10-10 | 2014-05-02 | Halbleitervorrichtung |
KR20140057576A KR20150042125A (ko) | 2013-10-10 | 2014-05-14 | 반도체장치 |
CN201410225111.2A CN104576710B (zh) | 2013-10-10 | 2014-05-26 | 半导体装置 |
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Application Number | Priority Date | Filing Date | Title |
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JP2013212639A JP6168961B2 (ja) | 2013-10-10 | 2013-10-10 | 半導体装置 |
Publications (3)
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JP2015076544A true JP2015076544A (ja) | 2015-04-20 |
JP2015076544A5 JP2015076544A5 (ja) | 2016-02-25 |
JP6168961B2 JP6168961B2 (ja) | 2017-07-26 |
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US (1) | US9871109B2 (ja) |
JP (1) | JP6168961B2 (ja) |
KR (1) | KR20150042125A (ja) |
CN (1) | CN104576710B (ja) |
DE (1) | DE102014208306B4 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016062944A (ja) * | 2014-09-16 | 2016-04-25 | 株式会社東芝 | 半導体装置 |
JP2018125415A (ja) * | 2017-02-01 | 2018-08-09 | 富士電機株式会社 | 半導体装置 |
US10347713B2 (en) | 2017-09-15 | 2019-07-09 | Kabushiki Kaisha Toshiba | Semiconductor device having a triple region resurf structure |
Families Citing this family (8)
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DE102016120301A1 (de) * | 2016-10-25 | 2018-04-26 | Infineon Technologies Ag | Leistungshalbleitervorrichtungs-Abschlussstruktur |
CN107068567B (zh) * | 2016-11-22 | 2020-01-24 | 中国电子科技集团公司第五十五研究所 | 一种射频vdmos晶体管的金属栅与场板结构及其制备方法 |
CN106783970B (zh) * | 2016-11-22 | 2020-05-08 | 中国电子科技集团公司第五十五研究所 | 一种射频vdmos晶体管的场板结构及其制备方法 |
US11152465B2 (en) * | 2017-08-31 | 2021-10-19 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device comprising surface semiconductor region for increased breakdown strength |
JP7024277B2 (ja) | 2017-09-20 | 2022-02-24 | 株式会社デンソー | 半導体装置 |
CN109713032B (zh) * | 2018-12-28 | 2020-12-18 | 电子科技大学 | 一种抗辐射半导体器件终端结构 |
CN110164955A (zh) * | 2019-05-28 | 2019-08-23 | 深圳市桦沣实业有限公司 | 一种横向变掺杂终端结构 |
KR102633398B1 (ko) * | 2021-05-27 | 2024-02-06 | 에스케이키파운드리 주식회사 | 반도체 소자를 위한 딥 트렌치 마스크 레이아웃 설계 방법 |
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JP5863574B2 (ja) * | 2012-06-20 | 2016-02-16 | 株式会社東芝 | 半導体装置 |
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2013
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- 2014-03-19 US US14/220,007 patent/US9871109B2/en active Active
- 2014-05-02 DE DE102014208306.0A patent/DE102014208306B4/de active Active
- 2014-05-14 KR KR20140057576A patent/KR20150042125A/ko not_active Application Discontinuation
- 2014-05-26 CN CN201410225111.2A patent/CN104576710B/zh active Active
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JP2009099863A (ja) * | 2007-10-18 | 2009-05-07 | Toshiba Corp | 半導体装置、及び半導体装置の製造方法 |
JP2010245281A (ja) * | 2009-04-06 | 2010-10-28 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2013135062A (ja) * | 2011-12-26 | 2013-07-08 | Mitsubishi Electric Corp | 半導体素子 |
JP2013172088A (ja) * | 2012-02-22 | 2013-09-02 | Toyota Motor Corp | 半導体装置 |
Cited By (3)
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JP2016062944A (ja) * | 2014-09-16 | 2016-04-25 | 株式会社東芝 | 半導体装置 |
JP2018125415A (ja) * | 2017-02-01 | 2018-08-09 | 富士電機株式会社 | 半導体装置 |
US10347713B2 (en) | 2017-09-15 | 2019-07-09 | Kabushiki Kaisha Toshiba | Semiconductor device having a triple region resurf structure |
Also Published As
Publication number | Publication date |
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DE102014208306B4 (de) | 2021-06-17 |
CN104576710A (zh) | 2015-04-29 |
CN104576710B (zh) | 2017-12-19 |
US20150102452A1 (en) | 2015-04-16 |
US9871109B2 (en) | 2018-01-16 |
JP6168961B2 (ja) | 2017-07-26 |
KR20150042125A (ko) | 2015-04-20 |
DE102014208306A1 (de) | 2015-04-16 |
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