JP2015046581A - 半導体装置及び該半導体装置を用いた表示装置 - Google Patents
半導体装置及び該半導体装置を用いた表示装置 Download PDFInfo
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- JP2015046581A JP2015046581A JP2014140256A JP2014140256A JP2015046581A JP 2015046581 A JP2015046581 A JP 2015046581A JP 2014140256 A JP2014140256 A JP 2014140256A JP 2014140256 A JP2014140256 A JP 2014140256A JP 2015046581 A JP2015046581 A JP 2015046581A
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- wiring
- oxide semiconductor
- insulating film
- transistor
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Abstract
Description
本実施の形態では、本発明の一態様の半導体装置について、図1乃至図3を用いて説明する。
図1(A)は、本発明の一態様の半導体装置の上面図であり、図1(B)は、図1(A)の一点鎖線A−B間及び一点鎖線C−D間における切断面の断面図に相当する。なお、図1(A)において、煩雑になることを避けるため、半導体装置の構成要素の一部(ゲート絶縁膜として機能する絶縁膜等)を省略して図示している。
ここで、図1(A)に示す接続部160の上面形状の変形例について、図3を用いて説明を行う。
図1(A)、(B)に示す本発明の一態様の半導体装置の作製方法について、図4乃至図6を用いて以下詳細に説明する。
図15(A)は、本発明の一態様の半導体装置の上面図であり、図15(B)は、図15(A)の一点鎖線A−B間及び一点鎖線C−D間における切断面の断面図に相当する。また、図15(C)は、図15(A)の一点鎖線E−F間における切断面の断面図に相当する。なお、図15(A)において、煩雑になることを避けるため、半導体装置の構成要素の一部(ゲート絶縁膜として機能する絶縁膜等)を省略して図示している。
図15(A)、(B)、(C)に示す本発明の一態様の半導体装置の作製方法について、図16及び図17を用いて以下説明する。
本実施の形態では、本発明の一態様の半導体装置について、図7乃至図9を用いて説明する。なお、図1乃至図6で示した符号については、同様の符号を用い、その繰り返しの説明は省略する。
本実施の形態では、本発明の一態様である半導体装置として、用いることのできるトランジスタの構造について、図10を用いて説明する。
本実施の形態では、本発明の一態様である半導体装置として、用いることのできるトランジスタの構造について、図11を用いて説明する。
本実施の形態では、実施の形態1のトランジスタ150に適用可能な酸化物半導体膜の一例について説明する。
CAAC−OS膜は、例えば、多結晶である酸化物半導体スパッタリング用ターゲットを用い、スパッタリング法によって成膜する。当該スパッタリング用ターゲットにイオンが衝突すると、スパッタリング用ターゲットに含まれる結晶領域がa−b面から劈開し、a−b面に平行な面を有する平板状またはペレット状のスパッタリング粒子として剥離することがある。この場合、当該平板状またはペレット状のスパッタリング粒子が、結晶状態を維持したまま基板に到達することで、CAAC−OS膜を成膜することができる。
本実施の形態では、本発明の一態様である半導体装置を表示装置に適用した一例について、図面を用いて説明する。なお、先の実施の形態に示す符号と同様の箇所、または同様の機能を有する部分については、同様の符号を付し、その詳細の説明は省略する。
本実施の形態では、本発明の一態様の半導体装置を適用した表示モジュール及び電子機器について、図13及び図14を用いて説明を行う。
図19(A)に示す半導体装置は、トランジスタ550と、接続部560とを有する。
図19(B)に示す半導体装置は、トランジスタ550と、接続部570とを有する。
まず、基板502を準備した。基板502としては、ガラス基板を用いた。その後、基板502上にゲート電極504a及び第1の配線504bとなる導電膜を形成した。該導電膜としては、スパッタリング法によりタングステン膜(W)を200nm形成した。その後、第1のパターニング工程及びエッチング工程を行い、ゲート電極504a及び第1の配線504bを形成した。
試料2の作製方法としては、試料1の作製方法と比較して、以下の点のみ異なる。
104a ゲート電極
104b 配線
106 絶縁膜
107 絶縁膜
108 絶縁膜
110 酸化物半導体膜
110a 酸化物半導体膜
110c 配線
111a 酸化物半導体膜
111b 酸化物膜
112 導電膜
112_2 配線
112_3 配線
112a ソース電極
112b ドレイン電極
112c 配線
112c_1 配線
114 絶縁膜
116 絶縁膜
118 絶縁膜
120 絶縁膜
122a 導電膜
122b 導電膜
122c ゲート電極
140 開口
140a 開口
142a 開口
142b 開口
142c 開口
142d 開口
142e 開口
144a 領域
144b 領域
148a レジストマスク
148b レジストマスク
148c レジストマスク
150 トランジスタ
151 トランジスタ
160 接続部
170 容量素子
200 画素部
202 画素
204 走査線駆動回路
206 信号線駆動回路
207 走査線
209 信号線
215 容量線
301 画素
322 液晶素子
410 酸化物半導体膜
410a 酸化物半導体膜
410b 酸化物半導体膜
410c 配線
412 導電膜
412a ソース電極
412b ドレイン電極
412c 配線
448a レジストマスク
448b レジストマスク
448c レジストマスク
448d レジストマスク
448e レジストマスク
450 トランジスタ
470 トランジスタ部
472 接続部
474 領域
475 領域
476 領域
478 領域
460 接続部
502 基板
504a ゲート電極
504b 配線
506 絶縁膜
507 絶縁膜
508 絶縁膜
510 酸化物半導体膜
512a ソース電極
512b ドレイン電極
512c 配線
512d 配線
514 絶縁膜
516 絶縁膜
518 絶縁膜
520 絶縁膜
522a 導電膜
522b 導電膜
540 開口
542a 開口
542b 開口
542c 開口
550 トランジスタ
560 接続部
570 接続部
5000 筐体
5001 表示部
5002 表示部
5003 スピーカ
5004 LEDランプ
5005 操作キー
5006 接続端子
5007 センサ
5008 マイクロフォン
5009 スイッチ
5010 赤外線ポート
5011 記録媒体読込部
5012 支持部
5013 イヤホン
5014 アンテナ
5015 シャッターボタン
5016 受像部
5017 充電器
8000 表示モジュール
8001 上部カバー
8002 下部カバー
8003 FPC
8004 タッチパネル
8005 FPC
8006 表示パネル
8007 バックライト
8008 光源
8009 フレーム
8010 プリント基板
8011 バッテリー
Claims (9)
- トランジスタ及び接続部を有する半導体装置であって、
前記トランジスタは、
ゲート電極と、
前記ゲート電極上に形成される第1の絶縁膜と、
前記第1の絶縁膜上に形成され、前記ゲート電極と重畳する位置に形成される酸化物半導体膜と、
前記酸化物半導体膜と電気的に接続されるソース電極及びドレイン電極と、を有し、
前記接続部は、
前記ゲート電極と同一表面上に形成される第1の配線と、
前記ソース電極及び前記ドレイン電極と同一表面上に形成される第2の配線と、
前記第1の配線と前記第2の配線を接続する第3の配線と、を有し、
前記第2の配線の端部は、
前記ソース電極及び前記ドレイン電極の端部よりも上端部と下端部の距離が長い
ことを特徴とする半導体装置。 - トランジスタ及び接続部を有する半導体装置であって、
前記トランジスタは、
ゲート電極と、
前記ゲート電極上に形成される第1の絶縁膜と、
前記第1の絶縁膜上に形成され、前記ゲート電極と重畳する位置に形成される酸化物半導体膜と、
前記酸化物半導体膜と電気的に接続されるソース電極及びドレイン電極と、を有し、
前記接続部は、
前記ゲート電極と同一表面上に形成される第1の配線と、
前記第1の配線上の前記第1の絶縁膜と、
前記第1の絶縁膜に設けられる第1の開口と、
前記ソース電極及び前記ドレイン電極と同一表面上に形成される第2の配線と、
前記第2の配線上の第2の絶縁膜と、
前記第2の絶縁膜に設けられる第2の開口と、
前記第1の開口と前記第2の開口を覆うように形成され、且つ前記第1の配線と前記第2の配線を接続する第3の配線と、を有し、
前記第2の配線の端部は、
前記ソース電極及び前記ドレイン電極の端部よりも上端部と下端部の距離が長い
ことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第2の配線、前記ソース電極及び前記ドレイン電極は、
少なくとも2層以上の積層構造である
ことを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一つにおいて、
前記第2の配線、前記ソース電極及び前記ドレイン電極は、
アルミニウム、クロム、銅、タンタル、チタン、モリブデン、タングステンの中から選択される一以上の元素を含む
ことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第2の配線の端部は、
角度の異なる2つの形状を有する
ことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第3の配線は、前記トランジスタに接続される画素電極と同一表面上に形成される
ことを特徴とする半導体装置。 - 請求項1、請求項2または請求項6のいずれか一つにおいて、
前記第3の配線は、
インジウムを含む酸化物である
ことを特徴とする半導体装置。 - 請求項1または請求項2において、
前記酸化物半導体膜は、
In−M−Zn酸化物(MはAl、Ga、Ge、Y、Zr、Sn、La、CeまたはHf)である
ことを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一つに記載の半導体装置を用いた表示装置。
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2014
- 2014-07-03 US US14/323,341 patent/US9293480B2/en active Active
- 2014-07-07 KR KR1020140084722A patent/KR102112187B1/ko active IP Right Grant
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US10367095B2 (en) | 2015-03-03 | 2019-07-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, method for manufacturing the same, or display device including the same |
JP2020145451A (ja) * | 2015-03-03 | 2020-09-10 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2016178299A (ja) * | 2015-03-17 | 2016-10-06 | 株式会社半導体エネルギー研究所 | 半導体装置、該半導体装置の作製方法、または該半導体装置を有する表示装置 |
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Also Published As
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US20170047354A1 (en) | 2017-02-16 |
JP2019068098A (ja) | 2019-04-25 |
JP2021119635A (ja) | 2021-08-12 |
US20160225796A1 (en) | 2016-08-04 |
KR20210060420A (ko) | 2021-05-26 |
JP2023052246A (ja) | 2023-04-11 |
JP6595084B2 (ja) | 2019-10-23 |
JP2020036016A (ja) | 2020-03-05 |
JP6882403B2 (ja) | 2021-06-02 |
US9490268B2 (en) | 2016-11-08 |
US20150014680A1 (en) | 2015-01-15 |
KR102112187B1 (ko) | 2020-05-18 |
KR102256372B1 (ko) | 2021-05-27 |
JP6460589B2 (ja) | 2019-01-30 |
KR20220110701A (ko) | 2022-08-09 |
JP7458517B2 (ja) | 2024-03-29 |
KR20200054158A (ko) | 2020-05-19 |
KR20150007231A (ko) | 2015-01-20 |
US9899423B2 (en) | 2018-02-20 |
JP2018157216A (ja) | 2018-10-04 |
US9293480B2 (en) | 2016-03-22 |
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