JP2014519201A5 - - Google Patents

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Publication number
JP2014519201A5
JP2014519201A5 JP2014511848A JP2014511848A JP2014519201A5 JP 2014519201 A5 JP2014519201 A5 JP 2014519201A5 JP 2014511848 A JP2014511848 A JP 2014511848A JP 2014511848 A JP2014511848 A JP 2014511848A JP 2014519201 A5 JP2014519201 A5 JP 2014519201A5
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JP
Japan
Prior art keywords
support substrate
undercut
insulating layer
semiconductor structure
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2014511848A
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English (en)
Japanese (ja)
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JP2014519201A (ja
JP6347744B2 (ja
Filing date
Publication date
Priority claimed from EP11305632.9A external-priority patent/EP2528089B1/en
Application filed filed Critical
Publication of JP2014519201A publication Critical patent/JP2014519201A/ja
Publication of JP2014519201A5 publication Critical patent/JP2014519201A5/ja
Application granted granted Critical
Publication of JP6347744B2 publication Critical patent/JP6347744B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014511848A 2011-05-23 2012-05-22 積層半導体構造における縦方向の電気接続の形成方法 Expired - Fee Related JP6347744B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161489015P 2011-05-23 2011-05-23
EP11305632.9 2011-05-23
EP11305632.9A EP2528089B1 (en) 2011-05-23 2011-05-23 Method for forming a vertical electrical connection in a layered semiconductor structure
US61/489,015 2011-05-23
PCT/EP2012/059503 WO2012160063A1 (en) 2011-05-23 2012-05-22 Method for forming a vertical electrical connection in a layered semiconductor structure

Publications (3)

Publication Number Publication Date
JP2014519201A JP2014519201A (ja) 2014-08-07
JP2014519201A5 true JP2014519201A5 (enExample) 2017-02-02
JP6347744B2 JP6347744B2 (ja) 2018-06-27

Family

ID=44789383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014511848A Expired - Fee Related JP6347744B2 (ja) 2011-05-23 2012-05-22 積層半導体構造における縦方向の電気接続の形成方法

Country Status (10)

Country Link
US (1) US9368397B2 (enExample)
EP (1) EP2528089B1 (enExample)
JP (1) JP6347744B2 (enExample)
KR (1) KR102014891B1 (enExample)
CN (1) CN103582942B (enExample)
CA (1) CA2836845C (enExample)
IL (1) IL229519B (enExample)
SG (1) SG194863A1 (enExample)
TW (1) TWI594387B (enExample)
WO (1) WO2012160063A1 (enExample)

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JP2015041691A (ja) * 2013-08-21 2015-03-02 株式会社東芝 半導体装置および半導体装置の製造方法
US9321635B2 (en) * 2013-11-28 2016-04-26 Solid State System Co., Ltd. Method to release diaphragm in MEMS device
WO2017209296A1 (ja) * 2016-06-03 2017-12-07 大日本印刷株式会社 貫通電極基板及びその製造方法、並びに実装基板
CN109835867B (zh) * 2017-11-24 2023-07-14 中芯国际集成电路制造(上海)有限公司 刻蚀溶液和刻蚀方法
CN109082216B (zh) * 2018-05-23 2019-12-27 同济大学 一种弹性导电膜及其制备方法
CN111180416B (zh) * 2018-11-13 2025-04-25 长鑫存储技术有限公司 半导体结构及其制备工艺以及半导体器件
CN110634837A (zh) * 2019-09-27 2019-12-31 哈尔滨理工大学 一种用于铜互联电路中的扩散阻挡层
US11276650B2 (en) * 2019-10-31 2022-03-15 Avago Technologies International Sales Pte. Limited Stress mitigation structure
JP7419877B2 (ja) * 2020-02-28 2024-01-23 セイコーエプソン株式会社 振動デバイス、電子機器および移動体
WO2022082697A1 (zh) * 2020-10-23 2022-04-28 华为技术有限公司 封装结构及封装结构的制备方法
JP7581915B2 (ja) * 2021-01-26 2024-11-13 セイコーエプソン株式会社 振動デバイスおよび振動デバイスの製造方法
CN113594132A (zh) * 2021-07-29 2021-11-02 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
FI20235748A1 (en) * 2023-06-28 2024-12-29 Canatu Finland Oy Functionalization of carbon nanostructures

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