JP2011527830A5 - - Google Patents

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Publication number
JP2011527830A5
JP2011527830A5 JP2011517428A JP2011517428A JP2011527830A5 JP 2011527830 A5 JP2011527830 A5 JP 2011527830A5 JP 2011517428 A JP2011517428 A JP 2011517428A JP 2011517428 A JP2011517428 A JP 2011517428A JP 2011527830 A5 JP2011527830 A5 JP 2011527830A5
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JP
Japan
Prior art keywords
metal
metal line
lines
line
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011517428A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011527830A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2009/004033 external-priority patent/WO2010005592A2/en
Publication of JP2011527830A publication Critical patent/JP2011527830A/ja
Publication of JP2011527830A5 publication Critical patent/JP2011527830A5/ja
Pending legal-status Critical Current

Links

JP2011517428A 2008-07-09 2009-07-08 導体間隙が縮小された超小型電子相互接続素子 Pending JP2011527830A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13445708P 2008-07-09 2008-07-09
US61/134,457 2008-07-09
PCT/US2009/004033 WO2010005592A2 (en) 2008-07-09 2009-07-08 Microelectronic interconnect element with decreased conductor spacing

Publications (2)

Publication Number Publication Date
JP2011527830A JP2011527830A (ja) 2011-11-04
JP2011527830A5 true JP2011527830A5 (enExample) 2012-09-13

Family

ID=41396280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011517428A Pending JP2011527830A (ja) 2008-07-09 2009-07-08 導体間隙が縮小された超小型電子相互接続素子

Country Status (4)

Country Link
US (4) US8461460B2 (enExample)
JP (1) JP2011527830A (enExample)
KR (1) KR101654820B1 (enExample)
WO (1) WO2010005592A2 (enExample)

Families Citing this family (13)

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US7914296B1 (en) * 2010-01-05 2011-03-29 Exatron, Inc. Interconnecting assembly with conductive lever portions on a support film
US9761489B2 (en) 2013-08-20 2017-09-12 Applied Materials, Inc. Self-aligned interconnects formed using substractive techniques
US9159670B2 (en) * 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
US9263349B2 (en) * 2013-11-08 2016-02-16 Globalfoundries Inc. Printing minimum width semiconductor features at non-minimum pitch and resulting device
US9609751B2 (en) * 2014-04-11 2017-03-28 Qualcomm Incorporated Package substrate comprising surface interconnect and cavity comprising electroless fill
CN105097758B (zh) * 2014-05-05 2018-10-26 日月光半导体制造股份有限公司 衬底、其半导体封装及其制造方法
ITUB20155408A1 (it) * 2015-11-10 2017-05-10 St Microelectronics Srl Substrato di packaging per dispositivi a semiconduttore, dispositivo e procedimento corrispondenti
US11063758B1 (en) 2016-11-01 2021-07-13 F5 Networks, Inc. Methods for facilitating cipher selection and devices thereof
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
CN109673112B (zh) * 2017-10-13 2021-08-20 鹏鼎控股(深圳)股份有限公司 柔性电路板以及柔性电路板的制作方法
US11018024B2 (en) * 2018-08-02 2021-05-25 Nxp Usa, Inc. Method of fabricating embedded traces
US11251117B2 (en) * 2019-09-05 2022-02-15 Intel Corporation Self aligned gratings for tight pitch interconnects and methods of fabrication
US11791320B2 (en) 2021-11-22 2023-10-17 Qualcomm Incorporated Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
US5072075A (en) * 1989-06-28 1991-12-10 Digital Equipment Corporation Double-sided hybrid high density circuit board and method of making same
JPH03110849A (ja) * 1989-09-25 1991-05-10 Nec Corp 半導体装置
US5440805A (en) 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5287619A (en) * 1992-03-09 1994-02-22 Rogers Corporation Method of manufacture multichip module substrate
US5509553A (en) * 1994-04-22 1996-04-23 Litel Instruments Direct etch processes for the manufacture of high density multichip modules
KR0157284B1 (ko) * 1995-05-31 1999-02-18 김광호 솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지
US5854128A (en) * 1996-04-29 1998-12-29 Micron Technology, Inc. Method for reducing capacitive coupling between conductive lines
US5846876A (en) * 1996-06-05 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit which uses a damascene process for producing staggered interconnect lines
US5995328A (en) * 1996-10-03 1999-11-30 Quantum Corporation Multi-layered integrated conductor trace array interconnect structure having optimized electrical parameters
US6222136B1 (en) * 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6137178A (en) * 1998-06-17 2000-10-24 Siemens Aktiengesellschaft Semiconductor metalization system and method
US6849923B2 (en) * 1999-03-12 2005-02-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of the same
JP3384995B2 (ja) * 2000-05-18 2003-03-10 株式会社ダイワ工業 多層配線基板及びその製造方法
JP3586190B2 (ja) * 2000-12-26 2004-11-10 株式会社東芝 半導体装置およびその製造方法
KR100400033B1 (ko) * 2001-02-08 2003-09-29 삼성전자주식회사 다층 배선 구조를 갖는 반도체 소자 및 그의 제조방법
US7670962B2 (en) 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
US20040011555A1 (en) * 2002-07-22 2004-01-22 Chiu Tsung Chin Method for manufacturing printed circuit board with stacked wires and printed circuit board manufacturing according to the mehtod
JP4133560B2 (ja) * 2003-05-07 2008-08-13 インターナショナル・ビジネス・マシーンズ・コーポレーション プリント配線基板の製造方法およびプリント配線基板
TWI286916B (en) * 2004-10-18 2007-09-11 Via Tech Inc Circuit structure
US20080001297A1 (en) * 2006-06-30 2008-01-03 Stefanie Lotz Laser patterning and conductive interconnect/materials forming techniques for fine line and space features

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