JP2021506141A5 - - Google Patents
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- JP2021506141A5 JP2021506141A5 JP2020548890A JP2020548890A JP2021506141A5 JP 2021506141 A5 JP2021506141 A5 JP 2021506141A5 JP 2020548890 A JP2020548890 A JP 2020548890A JP 2020548890 A JP2020548890 A JP 2020548890A JP 2021506141 A5 JP2021506141 A5 JP 2021506141A5
- Authority
- JP
- Japan
- Prior art keywords
- fin structure
- laminated
- channel material
- laminated fin
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000000463 material Substances 0.000 claims 40
- 238000000034 method Methods 0.000 claims 20
- 238000000151 deposition Methods 0.000 claims 6
- 230000000873 masking effect Effects 0.000 claims 6
- 230000008021 deposition Effects 0.000 claims 4
- 238000000926 separation method Methods 0.000 claims 3
- 239000000126 substance Substances 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762594352P | 2017-12-04 | 2017-12-04 | |
| US62/594,352 | 2017-12-04 | ||
| PCT/US2018/063623 WO2019112954A1 (en) | 2017-12-04 | 2018-12-03 | Method for controlling transistor delay of nanowire or nanosheet transistor devices |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021506141A JP2021506141A (ja) | 2021-02-18 |
| JP2021506141A5 true JP2021506141A5 (enExample) | 2021-04-01 |
| JP7089656B2 JP7089656B2 (ja) | 2022-06-23 |
Family
ID=66659359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020548890A Active JP7089656B2 (ja) | 2017-12-04 | 2018-12-03 | ナノワイヤ又はナノシートトランジスタデバイスのトランジスタ遅延を制御する方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US10714391B2 (enExample) |
| JP (1) | JP7089656B2 (enExample) |
| KR (2) | KR102449793B1 (enExample) |
| CN (1) | CN111566803B (enExample) |
| TW (1) | TWI775995B (enExample) |
| WO (1) | WO2019112954A1 (enExample) |
Families Citing this family (43)
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| US11404325B2 (en) | 2013-08-20 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and silicon germanium nanowire formation |
| KR102434993B1 (ko) * | 2015-12-09 | 2022-08-24 | 삼성전자주식회사 | 반도체 소자 |
| US12408431B2 (en) * | 2018-04-06 | 2025-09-02 | International Business Machines Corporation | Gate stack quality for gate-all-around field-effect transistors |
| US10825933B2 (en) * | 2018-06-11 | 2020-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-all-around structure and manufacturing method for the same |
| US20200295127A1 (en) * | 2019-03-13 | 2020-09-17 | Intel Corporation | Stacked transistors with different crystal orientations in different device strata |
| US11069679B2 (en) | 2019-04-26 | 2021-07-20 | International Business Machines Corporation | Reducing gate resistance in stacked vertical transport field effect transistors |
| US11037905B2 (en) * | 2019-04-26 | 2021-06-15 | International Business Machines Corporation | Formation of stacked vertical transport field effect transistors |
| WO2020232025A2 (en) * | 2019-05-13 | 2020-11-19 | Board Of Regents, The University Of Texas System | Catalyst influenced chemical etching for fabricating three-dimensional sram architectures and optical waveguides |
| US11710667B2 (en) * | 2019-08-27 | 2023-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same |
| US11557655B2 (en) * | 2019-10-11 | 2023-01-17 | Tokyo Electron Limited | Device and method of forming with three-dimensional memory and three-dimensional logic |
| CN112951912B (zh) * | 2019-12-10 | 2024-05-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| US11302692B2 (en) * | 2020-01-16 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same |
| US11368016B2 (en) | 2020-03-18 | 2022-06-21 | Mavagail Technology, LLC | ESD protection for integrated circuit devices |
| US11837280B1 (en) * | 2020-05-20 | 2023-12-05 | Synopsys, Inc. | CFET architecture for balancing logic library and SRAM bitcell |
| CN116325174A (zh) * | 2020-09-29 | 2023-06-23 | 华为技术有限公司 | 晶体管及其制作方法、集成电路、电子设备 |
| WO2022104489A1 (es) | 2020-11-20 | 2022-05-27 | Drovid Technologies | Método para transmitir y rastrear parámetros detectados por drones mediante (paas) con (ia). |
| CN116250077B (zh) * | 2020-11-24 | 2025-08-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及半导体结构的形成方法 |
| US11527535B2 (en) | 2021-01-21 | 2022-12-13 | International Business Machines Corporation | Variable sheet forkFET device |
| US11424120B2 (en) | 2021-01-22 | 2022-08-23 | Tokyo Electron Limited | Plasma etching techniques |
| CN115050646B (zh) * | 2021-03-08 | 2025-05-27 | 北方集成电路技术创新中心(北京)有限公司 | 半导体结构及其形成方法 |
| CN113130489A (zh) * | 2021-03-12 | 2021-07-16 | 中国科学院微电子研究所 | 一种半导体器件的制造方法 |
| CN115425076A (zh) * | 2021-05-14 | 2022-12-02 | 三星电子株式会社 | 纳米片晶体管器件及其形成方法 |
| US12170322B2 (en) * | 2021-05-14 | 2024-12-17 | Samsung Electronics Co., Ltd. | Devices including stacked nanosheet transistors |
| US11843001B2 (en) | 2021-05-14 | 2023-12-12 | Samsung Electronics Co., Ltd. | Devices including stacked nanosheet transistors |
| EP4089723A1 (en) * | 2021-05-14 | 2022-11-16 | Samsung Electronics Co., Ltd. | Devices including stacked nanosheet transistors |
| US12087770B2 (en) | 2021-08-05 | 2024-09-10 | International Business Machines Corporation | Complementary field effect transistor devices |
| KR102877120B1 (ko) * | 2021-08-13 | 2025-10-27 | 삼성전자주식회사 | 반도체 소자 |
| US12166037B2 (en) * | 2021-08-27 | 2024-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation layers in stacked semiconductor devices |
| US12113067B2 (en) | 2021-09-13 | 2024-10-08 | International Business Machines Corporation | Forming N-type and P-type horizontal gate-all-around devices |
| US11837604B2 (en) | 2021-09-22 | 2023-12-05 | International Business Machine Corporation | Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices |
| US12191208B2 (en) | 2021-09-23 | 2025-01-07 | International Business Machines Corporation | Dual strained semiconductor substrate and patterning |
| US20230117889A1 (en) * | 2021-10-15 | 2023-04-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
| KR20230063899A (ko) | 2021-10-28 | 2023-05-10 | 삼성전자주식회사 | 3차원 반도체 소자 및 그의 제조 방법 |
| US12255099B2 (en) | 2021-10-28 | 2025-03-18 | Samsung Electronics Co., Ltd. | Methods of forming fin-on-nanosheet transistor stacks |
| US12310062B2 (en) | 2021-11-11 | 2025-05-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including stacked transistors and methods of forming the same |
| US12439641B2 (en) * | 2021-11-19 | 2025-10-07 | Tokyo Electron Limited | Compact 3D design and connections with optimum 3D transistor stacking |
| US12324207B2 (en) | 2021-12-03 | 2025-06-03 | International Business Machines Corporation | Channel protection of gate-all-around devices for performance optimization |
| US20230207468A1 (en) * | 2021-12-28 | 2023-06-29 | International Business Machines Corporation | Stacked staircase cmos with buried power rail |
| US20230261090A1 (en) * | 2022-02-14 | 2023-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
| KR102893178B1 (ko) | 2022-05-17 | 2025-11-28 | 삼성전자주식회사 | 반도체 장치 |
| CN119522486A (zh) * | 2022-05-20 | 2025-02-25 | 东京毅力科创株式会社 | 在形成有源器件之前通过晶片键合来结合背面电力分配网络的顺序互补型fet |
| KR102809779B1 (ko) * | 2022-09-14 | 2025-05-16 | 연세대학교 산학협력단 | 재구성 가능한 양극성 트랜지스터 |
| US20240429102A1 (en) * | 2023-06-21 | 2024-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI283066B (en) * | 2004-09-07 | 2007-06-21 | Samsung Electronics Co Ltd | Field effect transistor (FET) having wire channels and method of fabricating the same |
| JP2011029503A (ja) | 2009-07-28 | 2011-02-10 | Toshiba Corp | 半導体装置 |
| US8551833B2 (en) * | 2011-06-15 | 2013-10-08 | International Businesss Machines Corporation | Double gate planar field effect transistors |
| DE112011106004B4 (de) | 2011-12-23 | 2017-07-13 | Intel Corporation | Halbleiterstruktur und Verfahren zum Herstellen einer CMOS-Nanodraht-Halbleiterstruktur |
| US9012284B2 (en) | 2011-12-23 | 2015-04-21 | Intel Corporation | Nanowire transistor devices and forming techniques |
| KR101678405B1 (ko) | 2012-07-27 | 2016-11-22 | 인텔 코포레이션 | 나노와이어 트랜지스터 디바이스 및 형성 기법 |
| KR102002380B1 (ko) * | 2012-10-10 | 2019-07-23 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| US9508796B2 (en) * | 2013-10-03 | 2016-11-29 | Intel Corporation | Internal spacers for nanowire transistors and method of fabrication thereof |
| CN106030815B (zh) * | 2014-03-24 | 2020-01-21 | 英特尔公司 | 制造纳米线器件的内部间隔体的集成方法 |
| US9818872B2 (en) * | 2015-06-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
| EP3127862B1 (en) | 2015-08-06 | 2018-04-18 | IMEC vzw | A method of manufacturing a gate-all-around nanowire device comprising two different nanowires |
| CN106531632B (zh) * | 2015-09-10 | 2020-01-03 | 中国科学院微电子研究所 | 堆叠纳米线mos晶体管制作方法 |
| CN108028274B (zh) * | 2015-09-10 | 2021-09-03 | 英特尔公司 | 半导体纳米线装置及其制造方法 |
| US9627540B1 (en) * | 2015-11-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9583399B1 (en) * | 2015-11-30 | 2017-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20170170268A1 (en) * | 2015-12-15 | 2017-06-15 | Qualcomm Incorporated | NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES |
| KR102416133B1 (ko) | 2016-01-11 | 2022-07-01 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| KR102360333B1 (ko) | 2016-02-18 | 2022-02-08 | 삼성전자주식회사 | 반도체 장치 |
| CN106960870B (zh) | 2016-01-11 | 2021-09-10 | 三星电子株式会社 | 半导体装置及其制造方法 |
| KR102323389B1 (ko) | 2016-03-02 | 2021-11-05 | 도쿄엘렉트론가부시키가이샤 | 튜닝가능한 선택도를 갖는 등방성 실리콘 및 실리콘-게르마늄 에칭 |
| WO2017171845A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Beaded fin transistor |
| US9660028B1 (en) * | 2016-10-31 | 2017-05-23 | International Business Machines Corporation | Stacked transistors with different channel widths |
-
2018
- 2018-11-29 US US16/204,605 patent/US10714391B2/en active Active
- 2018-12-03 JP JP2020548890A patent/JP7089656B2/ja active Active
- 2018-12-03 CN CN201880085673.8A patent/CN111566803B/zh active Active
- 2018-12-03 WO PCT/US2018/063623 patent/WO2019112954A1/en not_active Ceased
- 2018-12-03 KR KR1020207019360A patent/KR102449793B1/ko active Active
- 2018-12-03 KR KR1020227033658A patent/KR102550501B1/ko active Active
- 2018-12-04 TW TW107143538A patent/TWI775995B/zh active
-
2020
- 2020-06-10 US US16/898,014 patent/US10991626B2/en active Active
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