JP2013534370A - 半導体構造ならびに導電性材料を開口内に提供するための方法 - Google Patents

半導体構造ならびに導電性材料を開口内に提供するための方法 Download PDF

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JP2013534370A
JP2013534370A JP2013524857A JP2013524857A JP2013534370A JP 2013534370 A JP2013534370 A JP 2013534370A JP 2013524857 A JP2013524857 A JP 2013524857A JP 2013524857 A JP2013524857 A JP 2013524857A JP 2013534370 A JP2013534370 A JP 2013534370A
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copper
metal
containing material
openings
ruthenium
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JP2013534370A5 (https=
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ダブリュ． コリンズ，デール
リンドグレン，ジョー
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マイクロン テクノロジー， インク．
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/059—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by reflowing or applying pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Semiconductor Memories (AREA)
JP2013524857A 2010-08-20 2011-07-22 半導体構造ならびに導電性材料を開口内に提供するための方法 Pending JP2013534370A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/860,745 2010-08-20
US12/860,745 US9177917B2 (en) 2010-08-20 2010-08-20 Semiconductor constructions
PCT/US2011/045067 WO2012024056A2 (en) 2010-08-20 2011-07-22 Semiconductor constructions; and methods for providing electrically conductive material within openings

Publications (2)

Publication Number Publication Date
JP2013534370A true JP2013534370A (ja) 2013-09-02
JP2013534370A5 JP2013534370A5 (https=) 2014-12-04

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JP2013524857A Pending JP2013534370A (ja) 2010-08-20 2011-07-22 半導体構造ならびに導電性材料を開口内に提供するための方法

Country Status (7)

Country Link
US (3) US9177917B2 (https=)
JP (1) JP2013534370A (https=)
KR (1) KR20130044354A (https=)
CN (1) CN103081066A (https=)
SG (1) SG188236A1 (https=)
TW (1) TWI443775B (https=)
WO (1) WO2012024056A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015159183A (ja) * 2014-02-24 2015-09-03 東京エレクトロン株式会社 凹部にコバルトを供給する方法
JP2017212466A (ja) * 2012-03-28 2017-11-30 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ シームレスのコバルト間隙充填を可能にする方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8791018B2 (en) * 2006-12-19 2014-07-29 Spansion Llc Method of depositing copper using physical vapor deposition
US9177917B2 (en) 2010-08-20 2015-11-03 Micron Technology, Inc. Semiconductor constructions
US8859422B2 (en) * 2011-01-27 2014-10-14 Tokyo Electron Limited Method of forming copper wiring and method and system for forming copper film
JP5767570B2 (ja) * 2011-01-27 2015-08-19 東京エレクトロン株式会社 Ｃｕ配線の形成方法およびＣｕ膜の成膜方法、ならびに成膜システム
US8530320B2 (en) * 2011-06-08 2013-09-10 International Business Machines Corporation High-nitrogen content metal resistor and method of forming same
JP2014033139A (ja) * 2012-08-06 2014-02-20 Ulvac Japan Ltd デバイスの製造方法
JP2014086537A (ja) * 2012-10-23 2014-05-12 Ulvac Japan Ltd Ｃｕ層形成方法及び半導体装置の製造方法
CN105633005A (zh) * 2014-10-30 2016-06-01 中芯国际集成电路制造(上海)有限公司 铜互连结构的制作方法
CN107924868B (zh) 2015-08-12 2021-12-03 盛美半导体设备(上海)股份有限公司 加工互连结构使阻挡层侧壁凹进最小化的方法
US10892186B2 (en) * 2017-10-14 2021-01-12 Applied Materials, Inc. Integration of ALD copper with high temperature PVD copper deposition for BEOL interconnect
US10438846B2 (en) 2017-11-28 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Physical vapor deposition process for semiconductor interconnection structures
US12085504B2 (en) * 2018-07-18 2024-09-10 Halliburton Energy Services, Inc. Extraordinary IR-absorption in SiO2 thin films with a foreign or attenuating material applied
CN112201618A (zh) * 2020-09-30 2021-01-08 上海华力集成电路制造有限公司 一种优化衬垫层质量的方法
US12183631B2 (en) * 2021-07-02 2024-12-31 Applied Materials, Inc. Methods for copper doped hybrid metallization for line and via

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139092A (ja) * 1994-02-21 1996-05-31 Toshiba Corp 半導体装置及びその製造方法
JPH08148560A (ja) * 1994-11-16 1996-06-07 Nec Corp 半導体装置の配線構造及びその製造方法
JPH08316233A (ja) * 1994-06-21 1996-11-29 Toshiba Corp 半導体装置の製造方法
JPH1154612A (ja) * 1997-07-30 1999-02-26 Sony Corp 半導体装置およびその製造方法
JPH11186273A (ja) * 1997-12-19 1999-07-09 Ricoh Co Ltd 半導体装置及びその製造方法
JP2001007050A (ja) * 1999-04-19 2001-01-12 Kobe Steel Ltd 配線膜の形成方法
JP2001007049A (ja) * 1999-06-25 2001-01-12 Hitachi Ltd 半導体集積回路装置の製造方法およびその製造装置
JP2001250829A (ja) * 1999-12-29 2001-09-14 Hynix Semiconductor Inc 金属配線製造方法
JP2001284358A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP2008071850A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置の製造方法
JP2008141051A (ja) * 2006-12-04 2008-06-19 Ulvac Japan Ltd 半導体装置の製造方法及び半導体装置の製造装置
JP2009016520A (ja) * 2007-07-04 2009-01-22 Tokyo Electron Ltd 半導体装置の製造方法及び半導体装置の製造装置
JP2009105289A (ja) * 2007-10-24 2009-05-14 Tokyo Electron Ltd Ｃｕ配線の形成方法
JP2010153487A (ja) * 2008-12-24 2010-07-08 Panasonic Corp 半導体装置及びその製造方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090701A (en) 1994-06-21 2000-07-18 Kabushiki Kaisha Toshiba Method for production of semiconductor device
JP3386889B2 (ja) 1994-07-01 2003-03-17 マツダ株式会社 稼動管理装置
US5891803A (en) 1996-06-26 1999-04-06 Intel Corporation Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits
US6605197B1 (en) * 1997-05-13 2003-08-12 Applied Materials, Inc. Method of sputtering copper to fill trenches and vias
WO1999017358A1 (en) 1997-09-30 1999-04-08 Infineon Technologies Ag Improved gapfill of semiconductor structure using doped silicate glasses with multi-step deposition/anneal process
JP3815875B2 (ja) 1997-12-24 2006-08-30 株式会社カネカ 集積型薄膜光電変換装置の製造方法
US6068785A (en) 1998-02-10 2000-05-30 Ferrofluidics Corporation Method for manufacturing oil-based ferrofluid
JP3939426B2 (ja) 1998-03-13 2007-07-04 株式会社アルバック 銅系配線膜の加圧埋込方法
JP2000150653A (ja) * 1998-09-04 2000-05-30 Seiko Epson Corp 半導体装置の製造方法
US6292052B1 (en) 2000-03-06 2001-09-18 Tektronix, Inc. Output amplifier for a discrete filter-less optical reference receiver
US6399512B1 (en) * 2000-06-15 2002-06-04 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer
US6433402B1 (en) * 2000-11-16 2002-08-13 Advanced Micro Devices, Inc. Selective copper alloy deposition
TW518680B (en) * 2001-06-13 2003-01-21 Matsushita Electric Industrial Co Ltd Semiconductor device and method for fabricating the same
JP4555540B2 (ja) * 2002-07-08 2010-10-06 ルネサスエレクトロニクス株式会社 半導体装置
US8241701B2 (en) * 2005-08-31 2012-08-14 Lam Research Corporation Processes and systems for engineering a barrier surface for copper deposition
US7074721B2 (en) * 2003-04-03 2006-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming thick copper self-aligned dual damascene
DE10319135B4 (de) * 2003-04-28 2006-07-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Elektroplattieren von Kupfer über einer strukturierten dielektrischen Schicht, um die Prozess-Gleichförmigkeit eines nachfolgenden CMP-Prozesses zu verbessern
US7192495B1 (en) * 2003-08-29 2007-03-20 Micron Technology, Inc. Intermediate anneal for metal deposition
US6958291B2 (en) * 2003-09-04 2005-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect with composite barrier layers and method for fabricating the same
US8158532B2 (en) * 2003-10-20 2012-04-17 Novellus Systems, Inc. Topography reduction and control by selective accelerator removal
US7709958B2 (en) * 2004-06-18 2010-05-04 Uri Cohen Methods and structures for interconnect passivation
KR100602086B1 (ko) * 2004-07-13 2006-07-19 동부일렉트로닉스 주식회사 반도체 소자의 배선 형성방법
US7098128B2 (en) * 2004-09-01 2006-08-29 Micron Technology, Inc. Method for filling electrically different features
JP4595464B2 (ja) 2004-09-22 2010-12-08 ソニー株式会社 Ｃｍｏｓ固体撮像素子の製造方法
US7115985B2 (en) * 2004-09-30 2006-10-03 Agere Systems, Inc. Reinforced bond pad for a semiconductor device
US7367486B2 (en) 2004-09-30 2008-05-06 Agere Systems, Inc. System and method for forming solder joints
US20060240187A1 (en) * 2005-01-27 2006-10-26 Applied Materials, Inc. Deposition of an intermediate catalytic layer on a barrier layer for copper metallization
JP3904578B2 (ja) * 2005-04-08 2007-04-11 シャープ株式会社 半導体装置の製造方法
US20060251872A1 (en) * 2005-05-05 2006-11-09 Wang Jenn Y Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof
US7749896B2 (en) * 2005-08-23 2010-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same
US7666776B2 (en) * 2005-09-01 2010-02-23 Micron Technology, Inc. Methods of forming conductive structures
US7626815B2 (en) 2005-11-14 2009-12-01 Nvidia Corporation Drive bay heat exchanger
US8916232B2 (en) * 2006-08-30 2014-12-23 Lam Research Corporation Method for barrier interface preparation of copper interconnect
US7625815B2 (en) 2006-10-31 2009-12-01 International Business Machines Corporation Reduced leakage interconnect structure
US20080132050A1 (en) * 2006-12-05 2008-06-05 Lavoie Adrien R Deposition process for graded cobalt barrier layers
US20080296768A1 (en) 2006-12-14 2008-12-04 Chebiam Ramanan V Copper nucleation in interconnects having ruthenium layers
US7786006B2 (en) * 2007-02-26 2010-08-31 Tokyo Electron Limited Interconnect structures with a metal nitride diffusion barrier containing ruthenium and method of forming
US7859113B2 (en) * 2007-02-27 2010-12-28 International Business Machines Corporation Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method
US7858525B2 (en) * 2007-03-30 2010-12-28 Intel Corporation Fluorine-free precursors and methods for the deposition of conformal conductive films for nanointerconnect seed and fill
KR101629965B1 (ko) * 2007-04-09 2016-06-13 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 구리 배선용 코발트 질화물층 및 이의 제조방법
JP5377844B2 (ja) 2007-10-23 2013-12-25 Ｎｔｎ株式会社 固定式等速自在継手
US7799674B2 (en) * 2008-02-19 2010-09-21 Asm Japan K.K. Ruthenium alloy film for copper interconnects
US7964966B2 (en) * 2009-06-30 2011-06-21 International Business Machines Corporation Via gouged interconnect structure and method of fabricating same
US8232646B2 (en) * 2010-01-21 2012-07-31 International Business Machines Corporation Interconnect structure for integrated circuits having enhanced electromigration resistance
US20110204518A1 (en) * 2010-02-23 2011-08-25 Globalfoundries Inc. Scalability with reduced contact resistance
US9177917B2 (en) 2010-08-20 2015-11-03 Micron Technology, Inc. Semiconductor constructions
US8517769B1 (en) * 2012-03-16 2013-08-27 Globalfoundries Inc. Methods of forming copper-based conductive structures on an integrated circuit device

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139092A (ja) * 1994-02-21 1996-05-31 Toshiba Corp 半導体装置及びその製造方法
JPH08316233A (ja) * 1994-06-21 1996-11-29 Toshiba Corp 半導体装置の製造方法
JPH08148560A (ja) * 1994-11-16 1996-06-07 Nec Corp 半導体装置の配線構造及びその製造方法
JPH1154612A (ja) * 1997-07-30 1999-02-26 Sony Corp 半導体装置およびその製造方法
JPH11186273A (ja) * 1997-12-19 1999-07-09 Ricoh Co Ltd 半導体装置及びその製造方法
JP2001007050A (ja) * 1999-04-19 2001-01-12 Kobe Steel Ltd 配線膜の形成方法
JP2001007049A (ja) * 1999-06-25 2001-01-12 Hitachi Ltd 半導体集積回路装置の製造方法およびその製造装置
JP2001250829A (ja) * 1999-12-29 2001-09-14 Hynix Semiconductor Inc 金属配線製造方法
JP2001284358A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP2008071850A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置の製造方法
JP2008141051A (ja) * 2006-12-04 2008-06-19 Ulvac Japan Ltd 半導体装置の製造方法及び半導体装置の製造装置
JP2009016520A (ja) * 2007-07-04 2009-01-22 Tokyo Electron Ltd 半導体装置の製造方法及び半導体装置の製造装置
JP2009105289A (ja) * 2007-10-24 2009-05-14 Tokyo Electron Ltd Ｃｕ配線の形成方法
JP2010153487A (ja) * 2008-12-24 2010-07-08 Panasonic Corp 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017212466A (ja) * 2012-03-28 2017-11-30 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ シームレスのコバルト間隙充填を可能にする方法
JP2015159183A (ja) * 2014-02-24 2015-09-03 東京エレクトロン株式会社 凹部にコバルトを供給する方法

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US9177917B2 (en) 2015-11-03
CN103081066A (zh) 2013-05-01
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US10879113B2 (en) 2020-12-29
US20160056073A1 (en) 2016-02-25
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KR20130044354A (ko) 2013-05-02
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