JP2013222871A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013222871A JP2013222871A JP2012094401A JP2012094401A JP2013222871A JP 2013222871 A JP2013222871 A JP 2013222871A JP 2012094401 A JP2012094401 A JP 2012094401A JP 2012094401 A JP2012094401 A JP 2012094401A JP 2013222871 A JP2013222871 A JP 2013222871A
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- 229910052796 boron Inorganic materials 0.000 description 1
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Abstract
【解決手段】半導体基板SUBに形成される高耐圧トランジスタNTRは、第1導電型のウェル領域LPWと、ソース領域としての第1の不純物領域SRと、ドレイン領域としての第2の不純物領域DRとを備えている。上記半導体装置はさらに、第3の不純物領域PR3と、分離用ゲート電極SGとを備えている。第3の不純物領域PR3は、平面視における1対の第1の不純物領域SRの間に形成されており、ウェル領域LPWの電位を取り出すための領域である。分離用ゲート電極SGは、第1の不純物領域SRと第3の不純物領域PR3との間の主表面上に形成されている。
【選択図】図3
Description
(実施の形態1)
まず実施の形態の半導体基板SUBの主表面における各素子形成領域の配置について図1を用いて説明する。
図19は実施の形態1の図2に、図20は実施の形態1の図3に、図21は実施の形態1の図4に、それぞれ対応している。図19、図20(A)、(B)および図21を参照して、本実施の形態においては、実施の形態1の分離用ゲート電極SGの代わりに分離用絶縁膜SLSが形成されている点において、実施の形態1と異なっている。具体的には、半導体基板SUBの主表面上の、実施の形態1の分離用ゲート電極SGが形成される領域に、分離用ゲート電極SGと同様に、ソース領域SRとp型拡散領域PR3との間に、半導体基板SUBの主表面に分離用絶縁膜SLSが形成されている。
図22は実施の形態1の図2の高耐圧nMOSFETの形成領域に対応する。図22を参照して、図22は図2と基本的に同様の構成を有するが、ソース領域SRの延在する上下方向に関するソース領域SRの幅Bが、図2におけるソース領域SRの幅Aよりも広くなっている。すなわち図22においては互いに隣り合う1対のソース領域SRの間のバックゲート領域BGの間隔が図2に比べて長くなっている。
図23は実施の形態1の図2の高耐圧nMOSFETの形成領域に対応する。図23を参照して、図23は図2と基本的に同様の構成を有するが、ソース領域SRの延在する上下方向に関するソース領域SRの幅Cが、図2におけるソース領域SRの幅Aよりも狭くなっている。すなわち図23においては互いに隣り合う1対のソース領域SRの間のバックゲート領域BGの間隔が図2に比べて短くなっている。
最後に、図24〜図25を参照しながら、本実施の形態の要点について説明する。なお図24〜図25における各構成要素は、既述の同一の符号で記した構成要素と同様である。また図25(A)は図24のXXVA−XXVA線に沿う部分における概略断面図であり、図25(B)は図24のXXVB−XXVB線に沿う部分における概略断面図である。
Claims (7)
- 高耐圧トランジスタを備える半導体装置であり、
前記高耐圧トランジスタは、
主表面を有する半導体基板と、
前記主表面に形成された第1導電型のウェル領域と、
前記ウェル領域内の前記主表面に形成された、ソース電極を取り出すための複数の第2導電型の第1の不純物領域と、
前記主表面に、前記第1の不純物領域と隣り合うように形成された、ドレイン電極を取り出すための第2導電型の第2の不純物領域とを含み、
前記半導体装置は、
平面視における1対の前記第1の不純物領域の間であり、かつ前記ウェル領域内の前記主表面に形成された、前記ウェル領域の電位を取り出すための第1導電型の第3の不純物領域と、
前記第1の不純物領域と前記第3の不純物領域との間の前記主表面上に形成された分離用ゲート電極とを有する、半導体装置。 - 前記第1の不純物領域と前記第2の不純物領域とを跨ぐように前記主表面上に形成されるゲート電極をさらに有し、
前記分離用ゲート電極は前記ゲート電極と一体となるように形成される、請求項1に記載の半導体装置。 - 前記第3の不純物領域は、前記分離用ゲート電極および前記ゲート電極に囲まれる、請求項2に記載の半導体装置。
- 高耐圧トランジスタを備える半導体装置であり、
前記高耐圧トランジスタは、
主表面を有する半導体基板と、
前記主表面に形成された第1導電型のウェル領域と、
前記ウェル領域内の前記主表面に形成された、ソース電極を取り出すための複数の第2導電型の第1の不純物領域と、
前記主表面に、前記第1の不純物領域と隣り合うように形成された、ドレイン電極を取り出すための第2導電型の第2の不純物領域とを含み、
前記半導体装置は、
平面視における1対の前記第1の不純物領域の間であり、かつ前記ウェル領域内の前記主表面に形成された、前記ウェル領域の電位を取り出すための第1導電型の第3の不純物領域と、
前記第1の不純物領域と前記第3の不純物領域との間の前記主表面に形成された分離用絶縁膜とを有し、
前記分離用絶縁膜は、平面視において前記第1の不純物領域と前記第2の不純物領域とを結ぶ方向に交差する方向に、間隔をあけて複数配置される、半導体装置。 - 前記第1の不純物領域と前記第2の不純物領域とを跨ぐように前記主表面上に形成されるゲート電極をさらに有し、
前記第3の不純物領域は、前記分離用絶縁膜および前記ゲート電極に囲まれる、請求項4に記載の半導体装置。 - 前記第1および第2の不純物領域はn型不純物領域である、請求項1または4に記載の半導体装置。
- 平面視における1対の前記第1の不純物領域の間における前記ウェル領域は、前記第1の不純物領域と接している、請求項1または4に記載の半導体装置。
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JP2012094401A JP6184057B2 (ja) | 2012-04-18 | 2012-04-18 | 半導体装置 |
TW102111929A TWI578527B (zh) | 2012-04-18 | 2013-04-02 | 半導體裝置 |
US13/861,005 US8742497B2 (en) | 2012-04-18 | 2013-04-11 | Semiconductor device |
KR1020130042222A KR20130117698A (ko) | 2012-04-18 | 2013-04-17 | 반도체 장치 |
CN201310134392.6A CN103378158B (zh) | 2012-04-18 | 2013-04-18 | 半导体装置 |
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TWI578527B (zh) | 2017-04-11 |
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US8742497B2 (en) | 2014-06-03 |
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