JP2013175729A - 電界効果トランジスタ及びその製造方法 - Google Patents
電界効果トランジスタ及びその製造方法 Download PDFInfo
- Publication number
- JP2013175729A JP2013175729A JP2013037096A JP2013037096A JP2013175729A JP 2013175729 A JP2013175729 A JP 2013175729A JP 2013037096 A JP2013037096 A JP 2013037096A JP 2013037096 A JP2013037096 A JP 2013037096A JP 2013175729 A JP2013175729 A JP 2013175729A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- pattern
- gate electrode
- source
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 230000005669 field effect Effects 0.000 claims abstract description 49
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 42
- 125000006850 spacer group Chemical group 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 89
- 239000010410 layer Substances 0.000 claims description 59
- 238000002955 isolation Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 239000010955 niobium Substances 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 description 51
- 239000011229 interlayer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 230000003685 thermal hair damage Effects 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- GWAOOGWHPITOEY-UHFFFAOYSA-N 1,5,2,4-dioxadithiane 2,2,4,4-tetraoxide Chemical compound O=S1(=O)CS(=O)(=O)OCO1 GWAOOGWHPITOEY-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】上部面及び両側壁を有する活性パターンが提供された基板、前記活性パターンの上部面及び両側壁に近接しながら、前記活性パターンを横切るゲート電極、前記ゲート電極の側壁を覆うゲートスペーサ、前記ゲート電極の底面を覆うゲート誘電パターン、前記ゲート電極の一側で前記活性パターン上に形成されたソース電極、前記ゲート電極の他側で前記活性パターン上に形成されたドレーン電極、及び前記ソース及びドレーン電極の表面に各々形成されたシリサイドパターンを含み、前記ゲート誘電パターンは少なくとも1つの高誘電性薄膜を含み、前記ゲートスペーサは前記ゲート誘電パターンより低い誘電常数を有する。
【選択図】図1
Description
本発明の第2の目的は、高誘電膜−金属ゲートフィン型電界効果トランジスタのゲート電極の抵抗増加の抑制にある。
他の実施形態において第1及び第2マスクパターン110、120が活性パターンAP上に残る(例えば、第2マスクパターン120が上術の図4及び図5において除去されない)場合、第1及び第2マスクパターン110、120は後で除去されて活性フィンAFの上部面を露出する。
AP 活性パターン
GE ゲート電極
GO ゲート酸化膜
CHR チャネル領域
SDR ソース及びドレイン領域
99 ギャップ領域
100 基板(バルクシリコンウエハー)
110 第1マスクパターン
120 第2マスクパターン
105 素子分離トレンチ
130 素子分離パターン
140 ゲート絶縁膜
145 ゲート絶縁パターン(ゲート誘電パターン)
150 犠牲ゲート膜
152 第1犠牲膜
154 第2犠牲膜
160 犠牲ゲートパターン
162 第1犠牲パターン
164 第2犠牲パターン
170 ゲートスペーサ
180 ソース及びドレーンパターン
190 シリサイドパターン
200 下部層間絶縁膜
210 蝕刻停止パターン
220 ゲート電極
222 第1ゲート電極
224 第2ゲート電極
230 上部層間絶縁膜
240 コンタクトプラグ
250 配線
1300 電子装置
1310 制御器
1320 入出力装置
1330 メモリ
1340 無線インターフェイス
1350 バス
1400 メモリシステム
1410 メモリ素子
1420 メモリコントローラ
1430 ホスト
Claims (32)
- 上部面及び両側壁を有する活性パターンが提供された基板と、
前記活性パターンの上部面及び両側壁に近接しながら、前記活性パターンを横切るゲート電極と、
前記ゲート電極の側壁を覆うゲートスペーサと、
前記ゲート電極の底面を覆うゲート誘電パターンと、
前記ゲート電極の一側で、前記活性パターン上に形成されたソース電極と、
前記ゲート電極の他側で、前記活性パターン上に形成されたドレーン電極と、
前記ソース及びドレーン電極の表面に各々形成されたシリサイドパターンと、を含み、
前記ゲート誘電パターンは少なくとも1つの高誘電性薄膜を含み、前記ゲートスペーサは前記ゲート誘電パターンより低い誘電常数を有する、ことを特徴とする電界効果トランジスタ。 - 前記活性パターンは、前記ソース及びドレーン電極の間に介在し、前記ゲート電極の下方に位置する、チャネル領域を含み、
前記ゲート電極は前記チャネル領域の両側壁に近接する第1部分及び前記チャネル領域の上方に配置されて前記第1部分を連結する第2部分を含む、ことを特徴とする請求項1に記載の電界効果トランジスタ。 - 前記第1部分は前記第2部分より厚い厚さを有するように形成される、ことを特徴とする請求項2に記載の電界効果トランジスタ。
- 前記ゲート絶縁パターンは、前記ゲート電極の下方に配置されて、前記第1部分の底面及び側面、並びに前記第2部分の底面を覆う、ことを特徴とする請求項2に記載の電界効果トランジスタ。
- 前記基板はNMOS領域及びPMOS領域を含み、
前記ソース及びドレーン電極は、前記NMOS領域では前記チャネル領域の一部に引張性ストレイン(tensile strain)を印加するように構成され、前記PMOS領域では前記チャネル領域の一部に圧縮性ストレイン(compressive strain)を印加するように構成される、ことを特徴とする請求項2に記載の電界効果トランジスタ。 - 前記ソース及びドレーン電極は前記基板と異なる物質で形成される、ことを特徴とする請求項1に記載の電界効果トランジスタ。
- 前記ソース及びドレーン電極の上部面は前記ソース及びドレーン電極に近接する前記ゲート電極の底面より高い位置に形成されて、前記ソース及びドレーン電極と前記ゲート電極との対向する面は実質的に均一な間隔を有して互いに離隔される、ことを特徴とする請求項1に記載の電界効果トランジスタ。
- 前記対向する前記ソース及びドレーン電極の面と前記ゲート電極の面との間の部分は前記ゲートスペーサで満たされる、ことを特徴とする請求項7に記載の電界効果トランジスタ。
- 前記ゲート絶縁パターンは前記ゲート電極の底に局所的に形成されて、前記ゲート電極と実質的に同一の幅を有する、ことを特徴とする請求項1に記載の電界効果トランジスタ。
- 前記ゲート電極は第1ゲート電極及び第2ゲート電極を含み、
前記第1ゲート電極は前記ゲート絶縁パターンの上部面及び前記ゲートスペーサの内側壁をコンフォーマルに覆い、前記第2ゲート電極は前記第1ゲート電極の内側壁によって定義される空間を満たす、ことを特徴とする請求項1に記載の電界効果トランジスタ。 - 前記ゲート電極と前記ソース及びドレーン電極との間に介在する物質の誘電常数はシリコン窒化膜の誘電常数より低いか、或いは同一である、ことを特徴とする請求項1に記載の電界効果トランジスタ。
- 基板をパターニングして活性フィンを形成する段階と、
前記活性フィンを覆うゲート絶縁膜を形成する段階と、
前記ゲート絶縁膜上に、前記活性フィンを横切る犠牲ゲートパターンを形成する段階と、
前記犠牲ゲートパターンの側壁にゲートスペーサを形成する段階と、
前記犠牲ゲートパターンの一側にソース電極を形成する段階と、
前記犠牲ゲートパターンの他側にドレーン電極を形成する段階と、
前記ソース及びドレーン電極上に、各々、シリサイドパターンを形成する段階と、
前記犠牲ゲートパターンをゲートパターンで代替する段階と、を含む、ことを特徴とする電界効果トランジスタの製造方法。 - 前記ゲート絶縁膜は高誘電膜の中の少なくとも1つで形成され、
前記製造方法は、前記ゲート絶縁膜を形成した以後、そして前記シリサイドパターンを形成する以前に実施される熱処理段階をさらに含む、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 前記シリサイドパターンは、ニッケルシリサイド、コバルトシリサイド、タングステンシリサイド、チタニウムシリサイド、ニオビウムシリサイド、又はタンタルシリサイドの中の1つで形成される、ことを特徴とする請求項13に記載の電界効果トランジスタの製造方法。
- 前記ゲート絶縁膜は、前記ゲートパターンの代替の以後にも残存して前記電界効果トランジスタのゲート誘電膜の少なくとも一部分に使用される、ことを特徴とする請求項13に記載の電界効果トランジスタの製造方法。
- 前記ゲートスペーサは前記ゲート絶縁膜より低い誘電常数を有する、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。
- 前記活性フィンは前記犠牲ゲートパターンの下方に位置するチャネル領域及び前記チャネル領域の両側に位置するソース及びドレーン領域を含み、
前記犠牲ゲートパターンを形成する段階は前記ゲート絶縁膜を蝕刻して前記活性フィンの前記ソース及びドレーン領域を露出する段階をさらに含む、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 前記犠牲ゲートパターンを形成する段階は前記露出されたソース及びドレーン領域を蝕刻して、前記活性フィンのソース及びドレーン領域を、前記ソース及びドレーン領域の幅が上方に行くほど狭くなるテーパー構造にする段階をさらに含む、ことを特徴とする請求項17に記載の電界効果トランジスタの製造方法。
- 前記活性フィンは前記犠牲ゲートパターンの下方に位置するチャネル領域及び前記チャネル領域の両側に位置するソース及びドレーン領域を含み、
前記ゲートスペーサを形成する段階は前記活性フィンの前記ソース及びドレーン領域を露出する段階を含む、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 前記活性フィンを形成する段階は
前記基板をパターニングして素子分離トレンチを形成する段階と、
前記素子分離トレンチを満たす素子分離膜を形成する段階と、
前記素子分離膜の上部面をリセスして前記基板の上部面より低い上部面を有する素子分離パターンを形成する段階と、を含む、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 前記ゲート絶縁膜は単層又は多層構造に形成される、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。
- 前記基板はNMOS領域及びPMOS領域を含み、
前記ソース及びドレーン電極を形成する段階は
前記NMOS領域に引張性ストレイン(tensile strain)特性を提供するエピタキシァル層を形成する段階と、
前記PMOS領域に圧縮性ストレイン(compressive strain)特性を提供するエピタキシァル層を形成する段階と、を含む、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 前記犠牲ゲートパターンを前記ゲートパターンに代替する段階は
前記犠牲ゲートパターンを除去して前記ゲート絶縁膜を露出させる段階と、
前記露出されたゲート絶縁膜上にゲート膜を形成する段階と、を含み、
前記犠牲ゲートパターンを除去する段階は前記ゲート絶縁膜及び前記ゲートスペーサに対して蝕刻選択性を有する蝕刻レシピを使用して実施される、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 前記ゲート膜を形成する段階は
前記露出されたゲート絶縁膜上に仕事関数調節膜を形成する段階と、
前記仕事関数調節膜上に金属膜を形成する段階と、を含む、ことを特徴とする請求項23に記載の電界効果トランジスタの製造方法。 - 前記犠牲ゲートパターンは前記ゲート絶縁膜をコンフォーマルに覆う下部犠牲パターン及び前記下部犠牲パターン上に配置される上部犠牲パターンを含み、
前記犠牲ゲートパターンを前記ゲートパターンで代替する段階は
前記下部犠牲パターンを蝕刻停止膜に使用して前記上部犠牲パターンを選択的に除去する段階と、
前記ゲート絶縁膜に対して蝕刻選択性を有する蝕刻レシピを使用して前記下部犠牲パターンを選択的に除去する段階と、を含む、ことを特徴とする請求項12に記載の電界効果トランジスタの製造方法。 - 上部面及び両側壁を含む活性パターンが提供された基板と、
前記活性パターンの前記上部面及び前記側壁上に提供されたゲート電極と、
前記ゲート電極の一側で、前記活性パターン上に提供されたソース電極と、
前記ゲート電極の他側で、前記活性パターン上に提供されたドレーン電極と、
前記ゲート電極の内側壁と前記ソース及びドレーン電極の中での少なくとも1つの間に提供された絶縁物質と、
前記ゲート電極の底面上に提供された高誘電(high−k)ゲート絶縁パターンと、を含み、
前記絶縁物質は前記ゲート絶縁パターンより小さい誘電常数を有する、ことを特徴とする電界効果トランジスタ。 - 前記活性パターンは、前記ソース及びドレーン電極の間に介在し、前記ゲート電極の下方に位置する、チャネル領域を含み、
前記ゲート電極は前記チャネル領域の両側壁に近接する第1部分及び前記チャネル領域の上方に配置されて前記第1部分を連結する第2部分を含む、ことを特徴とする請求項26に記載の電界効果トランジスタ。 - 前記基板はNMOS領域及びPMOS領域を含み、
前記ソース及びドレーン電極は前記NMOS領域で前記チャネル領域の一部に引張性ストレイン(tensile strain)を印加するように構成され、前記PMOS領域で前記チャネル領域の一部に圧縮性ストレイン(compressive strain)を印加するように構成される、ことを特徴とする請求項27に記載の電界効果トランジスタ。 - 前記ソース及びドレーン電極の上部面は前記ソース及びドレーン電極に隣接する前記ゲート電極の底面より高い位置に形成されて、前記ソース及びドレーン電極と前記ゲート電極との対向する面は実質的に均一な間隔を有し、互に離隔される、ことを特徴とする請求項26に記載の電界効果トランジスタ。
- 前記ゲート絶縁パターンは前記ゲート電極の幅と実質的に同一の幅を有する、ことを特徴とする請求項26に記載の電界効果トランジスタ。
- 前記ゲート電極は第1ゲート電極及び第2ゲート電極を含み、
前記第1ゲート電極は前記ゲート絶縁パターンの上部面及び前記ゲートスペーサの内側壁をコンフォーマルに覆い、前記第2ゲート電極は前記第1ゲート電極の内側壁によって定義される空間を満たす、ことを特徴とする請求項26に記載の電界効果トランジスタ。 - 前記絶縁物質はシリコン窒化膜の誘電常数より低いか、或いは同一である誘電常数を有する、ことを特徴とする請求項26に記載の電界効果トランジスタ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2012-0019765 | 2012-02-27 | ||
KR1020120019765A KR101876793B1 (ko) | 2012-02-27 | 2012-02-27 | 전계효과 트랜지스터 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013175729A true JP2013175729A (ja) | 2013-09-05 |
JP2013175729A5 JP2013175729A5 (ja) | 2016-04-07 |
Family
ID=48950914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013037096A Pending JP2013175729A (ja) | 2012-02-27 | 2013-02-27 | 電界効果トランジスタ及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (3) | US9087723B2 (ja) |
JP (1) | JP2013175729A (ja) |
KR (1) | KR101876793B1 (ja) |
CN (1) | CN103296088B (ja) |
DE (1) | DE102013101248A1 (ja) |
TW (1) | TWI588942B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020021950A (ja) * | 2018-04-12 | 2020-02-06 | インテル・コーポレーション | 集積回路構造、及びコンピューティングデバイス |
US11563081B2 (en) | 2013-12-19 | 2023-01-24 | Daedalus Prime Llc | Self-aligned gate edge and local interconnect |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102049774B1 (ko) * | 2013-01-24 | 2019-11-28 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9214556B2 (en) * | 2013-08-09 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned dual-metal silicide and germanide formation |
WO2015094309A1 (en) * | 2013-12-19 | 2015-06-25 | Intel Corporation | Method of forming a wrap-around contact on a semicondcutor device |
CN104752224B (zh) * | 2013-12-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | FinFET器件及其制作方法 |
US9318384B2 (en) * | 2014-03-24 | 2016-04-19 | International Business Machines Corporation | Dielectric liner for a self-aligned contact via structure |
US9653461B2 (en) * | 2014-03-28 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with low source/drain contact resistance |
US9379185B2 (en) * | 2014-04-24 | 2016-06-28 | International Business Machines Corporation | Method of forming channel region dopant control in fin field effect transistor |
TWI615976B (zh) * | 2014-07-07 | 2018-02-21 | 聯華電子股份有限公司 | 鰭式場效電晶體及其製造方法 |
KR102276642B1 (ko) * | 2014-07-28 | 2021-07-15 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US9985112B2 (en) | 2015-02-06 | 2018-05-29 | International Business Machines Corporation | Sloped finFET with methods of forming same |
US20160247919A1 (en) * | 2015-02-23 | 2016-08-25 | Globalfoundries Inc. | Channel last replacement flow for bulk finfets |
KR102326316B1 (ko) * | 2015-04-10 | 2021-11-16 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR102376481B1 (ko) * | 2015-05-22 | 2022-03-21 | 삼성전자주식회사 | 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조방법 |
US9418897B1 (en) * | 2015-06-15 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wrap around silicide for FinFETs |
US9607838B1 (en) * | 2015-09-18 | 2017-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Enhanced channel strain to reduce contact resistance in NMOS FET devices |
US9722079B2 (en) * | 2015-10-15 | 2017-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
KR102427326B1 (ko) * | 2015-10-26 | 2022-08-01 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US10366989B2 (en) * | 2016-02-10 | 2019-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a contact bar over an S/D structure |
US9825036B2 (en) * | 2016-02-23 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for semiconductor device |
US10134600B2 (en) * | 2017-02-06 | 2018-11-20 | Lam Research Corporation | Dielectric contact etch |
US10516037B2 (en) * | 2017-06-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming shaped source/drain epitaxial layers of a semiconductor device |
US10672879B2 (en) | 2018-07-30 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming FinFET and gate-all-around FET with selective high-K oxide deposition |
DE102019118061A1 (de) * | 2018-09-19 | 2020-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selektive doppelsilizidherstellung unter verwendung eines maskenlosen herstellungsprozessablaufs |
US10998241B2 (en) | 2018-09-19 | 2021-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective dual silicide formation using a maskless fabrication process flow |
US11094826B2 (en) | 2018-09-27 | 2021-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
KR102198343B1 (ko) * | 2019-05-31 | 2021-01-04 | 연세대학교 산학협력단 | 전계 제어 발광 소자 |
CN113327857B (zh) * | 2020-02-28 | 2023-05-23 | 中芯国际集成电路制造(天津)有限公司 | 半导体结构及其形成方法 |
KR20210137276A (ko) * | 2020-05-07 | 2021-11-17 | 삼성전자주식회사 | 반도체 소자 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289871A (ja) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2008172209A (ja) * | 2006-12-11 | 2008-07-24 | Sony Corp | 半導体装置の製造方法および半導体装置 |
JP2009032955A (ja) * | 2007-07-27 | 2009-02-12 | Toshiba Corp | 半導体装置、およびその製造方法 |
JP2009094352A (ja) * | 2007-10-10 | 2009-04-30 | National Institute Of Advanced Industrial & Technology | 二重絶縁ゲート電界効果トランジスタ |
JP2010530623A (ja) * | 2007-06-20 | 2010-09-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 自己整合したソース/ドレイン領域を有するフィン型電界効果トランジスタ・デバイスおよびその形成方法 |
US20110147842A1 (en) * | 2009-12-23 | 2011-06-23 | Annalisa Cappellani | Multi-gate semiconductor device with self-aligned epitaxial source and drain |
Family Cites Families (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6413802B1 (en) | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6764884B1 (en) * | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
US7863674B2 (en) * | 2003-09-24 | 2011-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-gate transistors formed on bulk substrates |
KR100553703B1 (ko) * | 2003-10-01 | 2006-02-24 | 삼성전자주식회사 | 반도체 소자 및 그 형성 방법 |
US7105390B2 (en) * | 2003-12-30 | 2006-09-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
KR100598109B1 (ko) * | 2004-10-08 | 2006-07-07 | 삼성전자주식회사 | 비휘발성 기억 소자 및 그 형성 방법 |
KR100585178B1 (ko) | 2005-02-05 | 2006-05-30 | 삼성전자주식회사 | 금속 게이트 전극을 가지는 FinFET을 포함하는반도체 소자 및 그 제조방법 |
KR100693788B1 (ko) | 2005-06-30 | 2007-03-12 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
JP4880958B2 (ja) * | 2005-09-16 | 2012-02-22 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7402856B2 (en) * | 2005-12-09 | 2008-07-22 | Intel Corporation | Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same |
US7709312B2 (en) * | 2006-09-29 | 2010-05-04 | Intel Corporation | Methods for inducing strain in non-planar transistor structures |
JP2008282901A (ja) | 2007-05-09 | 2008-11-20 | Sony Corp | 半導体装置および半導体装置の製造方法 |
JP2008300384A (ja) * | 2007-05-29 | 2008-12-11 | Elpida Memory Inc | 半導体装置及びその製造方法 |
KR100897478B1 (ko) | 2007-10-25 | 2009-05-14 | 성균관대학교산학협력단 | 피넛 형상의 채널층을 갖는 전계 효과 트랜지스터 및 그제조방법 |
CN101593701B (zh) * | 2008-05-30 | 2011-05-04 | 中芯国际集成电路制造(北京)有限公司 | 应变nmos器件以及应变cmos器件的制造方法 |
WO2010032174A1 (en) | 2008-09-16 | 2010-03-25 | Nxp B.V. | Fin field effect transistor (finfet) |
KR101511933B1 (ko) * | 2008-10-31 | 2015-04-16 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터의 제조방법 |
JP5305969B2 (ja) | 2009-02-17 | 2013-10-02 | 株式会社東芝 | 半導体装置 |
US9054194B2 (en) * | 2009-04-29 | 2015-06-09 | Taiwan Semiconductor Manufactruing Company, Ltd. | Non-planar transistors and methods of fabrication thereof |
US8264021B2 (en) | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
US8472227B2 (en) | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US8716797B2 (en) | 2009-11-03 | 2014-05-06 | International Business Machines Corporation | FinFET spacer formation by oriented implantation |
US8134209B2 (en) * | 2009-12-17 | 2012-03-13 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US20110147831A1 (en) * | 2009-12-23 | 2011-06-23 | Steigerwald Joseph M | Method for replacement metal gate fill |
US8242560B2 (en) | 2010-01-15 | 2012-08-14 | International Business Machines Corporation | FinFET with thin gate dielectric layer |
US8709928B2 (en) | 2010-01-19 | 2014-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor fin device and method for forming the same using high tilt angle implant |
US8513107B2 (en) | 2010-01-26 | 2013-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Replacement gate FinFET devices and methods for forming the same |
US8399931B2 (en) * | 2010-06-30 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout for multiple-fin SRAM cell |
US8609495B2 (en) * | 2010-04-08 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid gate process for fabricating finfet device |
US8796759B2 (en) * | 2010-07-15 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
KR20120019765A (ko) | 2010-08-26 | 2012-03-07 | 김태형 | 에빙하우스의 망각곡선을 응용한 외국어 학습 장치 |
US8551829B2 (en) * | 2010-11-10 | 2013-10-08 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US20120306026A1 (en) * | 2011-05-31 | 2012-12-06 | International Business Machines Corporation | Replacement gate electrode with a tungsten diffusion barrier layer |
US8637359B2 (en) * | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
US8466027B2 (en) * | 2011-09-08 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide formation and associated devices |
US8557666B2 (en) * | 2011-09-13 | 2013-10-15 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits |
US8772149B2 (en) * | 2011-10-19 | 2014-07-08 | International Business Machines Corporation | FinFET structure and method to adjust threshold voltage in a FinFET structure |
CN103077947A (zh) * | 2011-10-26 | 2013-05-01 | 中国科学院微电子研究所 | 具有双金属栅的cmos器件及其制造方法 |
US9406518B2 (en) * | 2011-11-18 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate |
US8691681B2 (en) * | 2012-01-04 | 2014-04-08 | United Microelectronics Corp. | Semiconductor device having a metal gate and fabricating method thereof |
US8759184B2 (en) * | 2012-01-09 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and the methods for forming the same |
US9147765B2 (en) * | 2012-01-19 | 2015-09-29 | Globalfoundries Inc. | FinFET semiconductor devices with improved source/drain resistance and methods of making same |
US20130214364A1 (en) * | 2012-02-16 | 2013-08-22 | International Business Machines Corporation | Replacement gate electrode with a tantalum alloy metal layer |
US8722494B1 (en) * | 2012-11-01 | 2014-05-13 | International Business Machines Corporation | Dual gate finFET devices |
-
2012
- 2012-02-27 KR KR1020120019765A patent/KR101876793B1/ko active IP Right Grant
- 2012-12-19 TW TW101148405A patent/TWI588942B/zh active
-
2013
- 2013-01-30 US US13/754,063 patent/US9087723B2/en active Active
- 2013-02-08 DE DE102013101248A patent/DE102013101248A1/de active Granted
- 2013-02-27 JP JP2013037096A patent/JP2013175729A/ja active Pending
- 2013-02-27 CN CN201310061264.3A patent/CN103296088B/zh active Active
-
2015
- 2015-06-16 US US14/740,436 patent/US20150279960A1/en not_active Abandoned
-
2018
- 2018-07-03 US US16/026,749 patent/US20180331201A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289871A (ja) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2008172209A (ja) * | 2006-12-11 | 2008-07-24 | Sony Corp | 半導体装置の製造方法および半導体装置 |
JP2010530623A (ja) * | 2007-06-20 | 2010-09-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 自己整合したソース/ドレイン領域を有するフィン型電界効果トランジスタ・デバイスおよびその形成方法 |
JP2009032955A (ja) * | 2007-07-27 | 2009-02-12 | Toshiba Corp | 半導体装置、およびその製造方法 |
JP2009094352A (ja) * | 2007-10-10 | 2009-04-30 | National Institute Of Advanced Industrial & Technology | 二重絶縁ゲート電界効果トランジスタ |
US20110147842A1 (en) * | 2009-12-23 | 2011-06-23 | Annalisa Cappellani | Multi-gate semiconductor device with self-aligned epitaxial source and drain |
JP2013515356A (ja) * | 2009-12-23 | 2013-05-02 | インテル・コーポレーション | エピタキシャルソース/ドレインが自己整合したマルチゲート半導体デバイス |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11563081B2 (en) | 2013-12-19 | 2023-01-24 | Daedalus Prime Llc | Self-aligned gate edge and local interconnect |
JP2020021950A (ja) * | 2018-04-12 | 2020-02-06 | インテル・コーポレーション | 集積回路構造、及びコンピューティングデバイス |
Also Published As
Publication number | Publication date |
---|---|
CN103296088B (zh) | 2018-04-27 |
US20130221447A1 (en) | 2013-08-29 |
CN103296088A (zh) | 2013-09-11 |
US20180331201A1 (en) | 2018-11-15 |
DE102013101248A1 (de) | 2013-08-29 |
TWI588942B (zh) | 2017-06-21 |
US9087723B2 (en) | 2015-07-21 |
KR20130098004A (ko) | 2013-09-04 |
US20150279960A1 (en) | 2015-10-01 |
TW201336021A (zh) | 2013-09-01 |
KR101876793B1 (ko) | 2018-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2013175729A (ja) | 電界効果トランジスタ及びその製造方法 | |
KR102146469B1 (ko) | 반도체 장치 및 이의 제조 방법 | |
US9269813B2 (en) | Field effect transistor | |
US9679991B2 (en) | Method for manufacturing semiconductor device using gate portion as etch mask | |
US9412731B2 (en) | Semiconductor device | |
KR102021768B1 (ko) | 반도체 장치의 제조 방법 및 그 방법에 의해 제조된 반도체 장치 | |
KR102151768B1 (ko) | 반도체 장치 및 그 제조방법 | |
TW201511285A (zh) | 半導體元件以及提供該半導體元件的方法 | |
KR102060834B1 (ko) | 반도체 장치 및 그 제조방법 | |
KR102157839B1 (ko) | 핀-전계효과 트랜지스터의 소오스/드레인 영역들을 선택적으로 성장시키는 방법 | |
KR102276992B1 (ko) | 반도체 장치의 제조방법 | |
US20150064869A1 (en) | Method of forming Fin-FET | |
KR102392695B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
US9130040B2 (en) | FinFET semiconductor device and method of manufacturing the same | |
KR101974598B1 (ko) | 반도체 장치 및 그 제조방법 | |
US20130260531A1 (en) | Semiconductor device and method of fabricating the same | |
KR20130098006A (ko) | 모오스 전계효과 트랜지스터를 포함하는 반도체 장치 및 그 제조 방법 | |
KR102085082B1 (ko) | 반도체 장치 및 그 제조방법 | |
KR102443803B1 (ko) | 반도체 장치 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160223 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160223 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170313 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170404 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20171114 |