JP2013026625A - 半導体パッケージ及びその製造方法 - Google Patents

半導体パッケージ及びその製造方法 Download PDF

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Publication number
JP2013026625A
JP2013026625A JP2012159378A JP2012159378A JP2013026625A JP 2013026625 A JP2013026625 A JP 2013026625A JP 2012159378 A JP2012159378 A JP 2012159378A JP 2012159378 A JP2012159378 A JP 2012159378A JP 2013026625 A JP2013026625 A JP 2013026625A
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Japan
Prior art keywords
connection terminal
insulating film
chip
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012159378A
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English (en)
Japanese (ja)
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JP2013026625A5 (https=
Inventor
Young Lyong Kim
泳龍 金
Tae-Hun Kim
泰勳 金
Chul Yong Jang
▲チュル▼容 張
Jong-Ho Lee
種昊 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020120029739A external-priority patent/KR101936788B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2013026625A publication Critical patent/JP2013026625A/ja
Publication of JP2013026625A5 publication Critical patent/JP2013026625A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07131—Means for applying material, e.g. for deposition or forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2012159378A 2011-07-18 2012-07-18 半導体パッケージ及びその製造方法 Pending JP2013026625A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2011-0071016 2011-07-18
KR20110071016 2011-07-18
KR1020120029739A KR101936788B1 (ko) 2011-07-18 2012-03-23 반도체 패키지 및 그 제조 방법
KR10-2012-0029739 2012-03-23

Publications (2)

Publication Number Publication Date
JP2013026625A true JP2013026625A (ja) 2013-02-04
JP2013026625A5 JP2013026625A5 (https=) 2015-06-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012159378A Pending JP2013026625A (ja) 2011-07-18 2012-07-18 半導体パッケージ及びその製造方法

Country Status (4)

Country Link
US (2) US8970046B2 (https=)
JP (1) JP2013026625A (https=)
CN (1) CN102891136B (https=)
DE (1) DE102012212611A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2021241447A1 (https=) * 2020-05-26 2021-12-02

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015126102A (ja) * 2013-12-26 2015-07-06 株式会社東芝 半導体装置
US9305901B2 (en) * 2014-07-17 2016-04-05 Seagate Technology Llc Non-circular die package interconnect
CN104409448A (zh) * 2014-11-21 2015-03-11 三星半导体(中国)研究开发有限公司 半导体封装及其制造方法
JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
US10486548B2 (en) * 2016-01-13 2019-11-26 Ford Global Technologies, Llc Power inverter for a vehicle
US9875993B2 (en) * 2016-01-14 2018-01-23 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
KR102556327B1 (ko) * 2016-04-20 2023-07-18 삼성전자주식회사 패키지 모듈 기판 및 반도체 모듈
US20200066701A1 (en) * 2016-09-28 2020-02-27 Intel Corporation Stacked chip package having substrate interposer and wirebonds
KR102337647B1 (ko) 2017-05-17 2021-12-08 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102432379B1 (ko) * 2017-10-16 2022-08-12 삼성전자주식회사 반도체 소자
US10879225B2 (en) * 2018-10-24 2020-12-29 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing semiconductor package
US11024604B2 (en) * 2019-08-10 2021-06-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11171109B2 (en) * 2019-09-23 2021-11-09 Micron Technology, Inc. Techniques for forming semiconductor device packages and related packages, intermediate products, and methods
CN113964102A (zh) * 2019-11-29 2022-01-21 长江存储科技有限责任公司 芯片封装结构及其制造方法
US11373956B2 (en) 2020-01-14 2022-06-28 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11647633B2 (en) 2020-07-13 2023-05-09 Micron Technology, Inc. Methods used in forming integrated circuitry comprising a stack comprising vertically-alternating first tiers and second tiers with the stack comprising a cavity therein that comprises a stair-step structure
US11942430B2 (en) * 2021-07-12 2024-03-26 Micron Technology, Inc. Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules
US12500148B2 (en) 2021-07-30 2025-12-16 Stmicroelectronics S.R.L. Method of coupling semiconductor dice, tool for use therein and corresponding semiconductor device
US12525512B2 (en) * 2021-07-30 2026-01-13 Stmicroelectronics S.R.L. Method of coupling semiconductor dice and corresponding semiconductor device
CN114093822B (zh) * 2021-11-03 2025-10-31 长江存储科技有限责任公司 半导体封装结构及制备方法、待封装芯片的制备方法
US20230260949A1 (en) * 2022-02-16 2023-08-17 Western Digital Technologies, Inc. Semiconductor Device with Protective Layer
US12374647B2 (en) * 2022-05-12 2025-07-29 Renesas Electronics Corporation Semiconductor device including chip-to-chip bonding
US12374620B2 (en) * 2022-06-01 2025-07-29 Micron Technology, Inc. Memory circuitry and method used in forming memory circuitry
CN115642142A (zh) * 2022-10-19 2023-01-24 深圳市汇顶科技股份有限公司 芯片堆叠封装结构及封装方法
US20250006701A1 (en) * 2023-06-29 2025-01-02 Western Digital Technologies, Inc. Semiconductor die stacking architecture and connection method therefore

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291721A (ja) * 2000-04-06 2001-10-19 Nec Corp 配線構造、導電パターンの形成方法、半導体装置および半導体装置の製造方法
JP2003068934A (ja) * 2001-08-30 2003-03-07 Ibiden Co Ltd 半導体チップ
JP2004063569A (ja) * 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004063808A (ja) * 2002-07-29 2004-02-26 Matsushita Electric Works Ltd 半導体装置のパッケージ構造とその製造方法
JP2004179288A (ja) * 2002-11-26 2004-06-24 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法
US6756252B2 (en) * 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
JP2007059851A (ja) * 2005-08-26 2007-03-08 Toyota Industries Corp 半導体装置の製造方法
US20080303131A1 (en) * 2007-06-11 2008-12-11 Vertical Circuits, Inc. Electrically interconnected stacked die assemblies
JP2009081310A (ja) * 2007-09-26 2009-04-16 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2010050286A (ja) * 2008-08-21 2010-03-04 Toshiba Corp 半導体装置
WO2010087336A1 (ja) * 2009-01-27 2010-08-05 パナソニック電工株式会社 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法
JP2011243790A (ja) * 2010-05-19 2011-12-01 Panasonic Electric Works Co Ltd 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
JP3612310B2 (ja) * 2002-06-18 2005-01-19 株式会社東芝 半導体装置
US20040108217A1 (en) 2002-12-05 2004-06-10 Dubin Valery M. Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby
CN100499053C (zh) 2003-02-28 2009-06-10 西门子公司 用于具有遵循表面轮廓的电绝缘材料层的功率半导体的布线工艺
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
KR20070048952A (ko) 2005-11-07 2007-05-10 삼성전자주식회사 내부 접속 단자를 갖는 멀티 칩 패키지
TWI358815B (en) * 2006-09-12 2012-02-21 Chipmos Technologies Inc Stacked chip package structure with lead-frame hav
KR100825793B1 (ko) * 2006-11-10 2008-04-29 삼성전자주식회사 배선을 구비하는 배선 필름, 상기 배선 필름을 구비하는반도체 패키지 및 상기 반도체 패키지의 제조방법
KR100920039B1 (ko) 2007-06-21 2009-10-07 주식회사 하이닉스반도체 적층형 반도체 패키지 및 이의 제조 방법
KR101013545B1 (ko) 2007-07-26 2011-02-14 주식회사 하이닉스반도체 스택 패키지 및 그의 제조방법
US20100090347A1 (en) * 2008-10-09 2010-04-15 Saylor Stephen D Apparatus and method for contact formation in semiconductor devices

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291721A (ja) * 2000-04-06 2001-10-19 Nec Corp 配線構造、導電パターンの形成方法、半導体装置および半導体装置の製造方法
JP2003068934A (ja) * 2001-08-30 2003-03-07 Ibiden Co Ltd 半導体チップ
US6756252B2 (en) * 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
JP2004063569A (ja) * 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004063808A (ja) * 2002-07-29 2004-02-26 Matsushita Electric Works Ltd 半導体装置のパッケージ構造とその製造方法
JP2004179288A (ja) * 2002-11-26 2004-06-24 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法
JP2007059851A (ja) * 2005-08-26 2007-03-08 Toyota Industries Corp 半導体装置の製造方法
US20080303131A1 (en) * 2007-06-11 2008-12-11 Vertical Circuits, Inc. Electrically interconnected stacked die assemblies
JP2009081310A (ja) * 2007-09-26 2009-04-16 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2010050286A (ja) * 2008-08-21 2010-03-04 Toshiba Corp 半導体装置
WO2010087336A1 (ja) * 2009-01-27 2010-08-05 パナソニック電工株式会社 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法
JP2011243790A (ja) * 2010-05-19 2011-12-01 Panasonic Electric Works Co Ltd 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2021241447A1 (https=) * 2020-05-26 2021-12-02
JP7709435B2 (ja) 2020-05-26 2025-07-16 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
US20150155199A1 (en) 2015-06-04
DE102012212611A8 (de) 2013-05-08
DE102012212611A1 (de) 2013-03-07
US20130020720A1 (en) 2013-01-24
US8970046B2 (en) 2015-03-03
US9281235B2 (en) 2016-03-08
CN102891136B (zh) 2017-06-23
CN102891136A (zh) 2013-01-23

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